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[209.132.180.67]) by mx.google.com with ESMTP id x15si3838732eda.53.2019.09.25.10.42.13; Wed, 25 Sep 2019 10:42:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-leds-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=hoOPcvuu; spf=pass (google.com: best guess record for domain of linux-leds-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-leds-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2408401AbfIYRmN (ORCPT + 1 other); Wed, 25 Sep 2019 13:42:13 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:58562 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732339AbfIYRlU (ORCPT ); Wed, 25 Sep 2019 13:41:20 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x8PHfGjx055227; Wed, 25 Sep 2019 12:41:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1569433276; bh=UDFcTS6C48EriDoiPf6gaHVdwzTyvBdisepMFN/NjOI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hoOPcvuu6WuC2rnUBHanY4OZSBsq2qWbjzAkA1NnQx9/l4cPVdjpeANlfOykiybpP abSnsU4xEES74CRj0scE0NEwxwaz/ve+2wojq6BjqXByumIRH3dFXhoIakivOMoN/H YRDG8+Z3fL35eY0nLHZHkadgmh2npyaQBq911XwM= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8PHfGnJ018223; Wed, 25 Sep 2019 12:41:16 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 25 Sep 2019 12:41:09 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 25 Sep 2019 12:41:16 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x8PHfGm5129605; Wed, 25 Sep 2019 12:41:16 -0500 From: Dan Murphy To: , CC: , , Dan Murphy Subject: [PATCH v9 08/15] dt: bindings: lp55xx: Be consistent in the document with LED Date: Wed, 25 Sep 2019 12:46:09 -0500 Message-ID: <20190925174616.3714-9-dmurphy@ti.com> X-Mailer: git-send-email 2.22.0.214.g8dca754b1e In-Reply-To: <20190925174616.3714-1-dmurphy@ti.com> References: <20190925174616.3714-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-leds-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org Update the document to be consistent in case when using LED. This should be capital throughout the document. Signed-off-by: Dan Murphy --- Documentation/devicetree/bindings/leds/leds-lp55xx.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.22.0.214.g8dca754b1e diff --git a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt index 1b66a413fb9d..bfe2805c5534 100644 --- a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt +++ b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt @@ -1,4 +1,4 @@ -Binding for TI/National Semiconductor LP55xx Led Drivers +Binding for TI/National Semiconductor LP55xx LED Drivers Required properties: - compatible: one of @@ -12,8 +12,8 @@ Required properties: - clock-mode: Input clock mode, (0: automode, 1: internal, 2: external) Each child has own specific current settings -- led-cur: Current setting at each led channel (mA x10, 0 if led is not connected) -- max-cur: Maximun current at each led channel. +- led-cur: Current setting at each LED channel (mA x10, 0 if LED is not connected) +- max-cur: Maximun current at each LED channel. Optional properties: - enable-gpio: GPIO attached to the chip's enable pin