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Thu, 10 Apr 2025 23:38:33 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 16/16] iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support Date: Thu, 10 Apr 2025 23:37:55 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F2:EE_|SN7PR12MB8132:EE_ X-MS-Office365-Filtering-Correlation-Id: b0d62232-6d1b-4e65-d974-08dd78c382d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: tYGHHOoWT4GfFTmXzgTXstoCSnU1VBCCePXgCeikAi+errbZcY9VS+NGR9+ojCZmLVae+rIGLLlcKfa7v/PKi96+w6MgUlYDN2VyTLoJ5emjHnzE2cqhbrC1jDM+h2D32LdH56EYNdnKDkW/intNJt8LA7E89JyNXp5Rk+ei260CxrHPzp9g9bWY6mFTPALMgJvYzpUr4KlFts4zcPlWW04L/YQsspgA6QbWNS2OH+ETkhVfDESiJuyrrygdI8pp3D2m6aMGj9tdLoi3MwB4/e6gr1UfePZbvd3Li0iFlPsPJWsr3xRYjslMa46NqJmUWrUAiKBZSNkmOADxXmBshNGpsHWjtdiySy93rEEeSn6ayFpSUmx8t5s0smSWGwTzsnb73FdnCnaPfvDmskR6BE7YIg2QMF5UAixsFt57c+njOJJpqiG+dbdFLadhrTO5ngH5gSMneURPVeso6H8+2rDBMF/XvIpp6yZt5cv41DmUgJWNoUAVJ8le++VLcYomltqE2u/s+COQswEINL307LsuOGbkCqBK+mdLsCop3KVt2qW1CsYIQeAhvLcHuzWR7AqrCbdHE2f80kzqV62gPKmrARBynndfJ+rsTM/N34j07ZNoug02cRrmDd0xJic6Em2UOiqi3I55EYWWi/+12nIVPBw79PKq9QKQPpfVbDfyapd/IeWVREpa2Vj/NXxnTW/tdtZ2PK5Re7D2gwDkb5OnCp9Vang6htDYT4gXxUMDR8RUwCx3jDRlQ9ftgbzoIo9XNheGdUSYg1WcTBEv/4yi9TiRL8ypUMhzeOlbinbDxbpdnaJpQLXsFAcTpp9xLSvuXokTbfrJnkHqZmMyd+oJseK8DGzL8S6BxUJEwQZw/1SnfrccUlegRUFjHB/8ZzxMhe0lLXwv5n64euOB9IqNamgeEUCsuWBfeNtKoMprlmIVr9exrNksDtXeRjdwbnskagEfBrnFGkrSugmjQV8LeGPdvG+l2qBoNGNpBr2NoTLu3dKxR1GF9YVMTVR3lrWBDhx5EdDUAv25WvIzUbsAHDNhVJN2HEnhrdjV3uKC9jdIuXqUtmubhQP+VCCRBt3ohEkmxl5/Z1GYSuPlgZq7TMhuuMH7cr9y18ggNogGDavxrv0IrHPApZCdJZ2El39BNsNeYutLJJsT3bVZlmW2PP4ui9gDVJU7NY3Ns7T0MqE/Pf1I1aPTk4Knu5lPu3eqb2o64XZ0V5D+2LolKhuqstHouBnozYbyn2SiKmR0CKAimsJbwRxpieziApUjy/B2yN3/xK9f8KJhmV75G15bzi1LdLiUSPlE+IWDLEDdPqgvx06GG9BqY2fTx2EdP44u3gJYMEnlIO4HBdQ90KmkEVOc4W0WRq6wJErFAVn2l+Q597kDFuhozLXXtgvKH3YX+Y+tK0CyDqB4BqnERucx51Ok7pH4zBNyl2jHQgOadm2DRYOfQdyc/pGL93saipQz5AVUmoMhmXb0MQGG8AZ7T2+g89y5rvF8ASUMTUOrV9tLZcibHf+3EKO6RONy X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Simply report the two 64-bit LVCMDQ_ERR_MAPs register values. Signed-off-by: Nicolin Chen --- include/uapi/linux/iommufd.h | 15 +++++++++++++ .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 22 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index ce20f038b56b..dd3f6c021024 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1100,10 +1100,12 @@ struct iommufd_vevent_header { * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue + * @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ */ enum iommu_veventq_type { IOMMU_VEVENTQ_TYPE_DEFAULT = 0, IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2, }; /** @@ -1127,6 +1129,19 @@ struct iommu_vevent_arm_smmuv3 { __aligned_le64 evt[4]; }; +/** + * struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV Virtual IRQ + * (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV) + * @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian. + * (Refer to register LVCMDQ_ERR_MAPs per VINTF ) + * + * The 128-bit register values from HW exclusively reflect the error bits for a + * Virtual Interface represented by a vIOMMU object. Read and report directly. + */ +struct iommu_vevent_tegra241_cmdqv { + __aligned_le64 lvcmdq_err_map[2]; +}; + /** * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) * @size: sizeof(struct iommu_veventq_alloc) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index b778739f845a..dafaeff8d51d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -292,6 +292,20 @@ static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval) /* ISR Functions */ +static void tegra241_vintf_user_handle_error(struct tegra241_vintf *vintf) +{ + struct iommufd_viommu *viommu = &vintf->vsmmu.core; + struct iommu_vevent_tegra241_cmdqv vevent_data; + int i; + + for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) + vevent_data.lvcmdq_err_map[i] = + readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); + + iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + &vevent_data, sizeof(vevent_data)); +} + static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) { int i; @@ -337,6 +351,14 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) vintf_map &= ~BIT_ULL(0); } + /* Handle other user VINTFs and their LVCMDQs */ + while (vintf_map) { + unsigned long idx = __ffs64(vintf_map); + + tegra241_vintf_user_handle_error(cmdqv->vintfs[idx]); + vintf_map &= ~BIT_ULL(idx); + } + return IRQ_HANDLED; }