From patchwork Sat Sep 2 12:59:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 719821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2367C71153 for ; Sat, 2 Sep 2023 12:52:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352223AbjIBMws (ORCPT ); Sat, 2 Sep 2023 08:52:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352206AbjIBMwq (ORCPT ); Sat, 2 Sep 2023 08:52:46 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF49E1702; Sat, 2 Sep 2023 05:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693659162; x=1725195162; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nK8zunl6sSytTPWcLV67OItdVTMIy0Fmekb7+APwIxA=; b=ifZPalusNqL/vcwItmTGZAMUq1DYL2rdaduGPOCZOtsf9vunpjHtHiBO aQE9Mqm8rwJGDb/DJWQZkahrFKHBq+o5ciwMmSFIIpQvQ+Vgh7hqopI1k DJ2Cytc72aQdeMIo0mHE8yfALLe12P7+K+ko7hGxypGTqRS7tiBNSXZ56 7ytgWFe9hd/rkdOA2s0ooE2TmiaZudEkfANctj4jBnv9V8jqxwq9dd2KZ 2cNxHV6tEEK3T3Jcei2+/4JxlNdMWzuBKqV3aA8DkUBhzp19F+JpDqHxn BmfyNKts2wY2ENcTAn1/NBYEWvrPwGcn+utj47V+k+oQ38fkXX++CYL+f w==; X-IronPort-AV: E=McAfee;i="6600,9927,10821"; a="366599316" X-IronPort-AV: E=Sophos;i="6.02,222,1688454000"; d="scan'208";a="366599316" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2023 05:52:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10821"; a="855022099" X-IronPort-AV: E=Sophos;i="6.02,222,1688454000"; d="scan'208";a="855022099" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Sep 2023 05:52:33 -0700 From: Haibo Xu Cc: xiaobo55x@gmail.com, haibo1.xu@intel.com, ajones@ventanamicro.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Guo Ren , Conor Dooley , wchen , Greentime Hu , Sean Christopherson , Ricardo Koller , Vishal Annapurve , Vitaly Kuznetsov , Aaron Lewis , David Matlack , Mingwei Zhang , Ackerley Tng , Jim Mattson , Vipin Sharma , Maxim Levitsky , Peter Gonda , Like Xu , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= , Thomas Huth , David Woodhouse , Michal Luczaj , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: [PATCH v2 4/8] KVM: riscv: selftests: Switch to use macro from csr.h Date: Sat, 2 Sep 2023 20:59:26 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Signed-off-by: Haibo Xu --- tools/testing/selftests/kvm/include/riscv/processor.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h index 5b62a3d2aa9b..6810c887fadc 100644 --- a/tools/testing/selftests/kvm/include/riscv/processor.h +++ b/tools/testing/selftests/kvm/include/riscv/processor.h @@ -8,6 +8,7 @@ #define SELFTEST_KVM_PROCESSOR_H #include "kvm_util.h" +#include #include static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, @@ -95,12 +96,8 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t idx, #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) #define SATP_MODE_39 _AC(0x8000000000000000, UL) #define SATP_MODE_48 _AC(0x9000000000000000, UL) -#define SATP_ASID_BITS 16 -#define SATP_ASID_SHIFT 44 -#define SATP_ASID_MASK _AC(0xFFFF, UL) #define SBI_EXT_EXPERIMENTAL_START 0x08000000 #define SBI_EXT_EXPERIMENTAL_END 0x08FFFFFF