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Wed, 7 Aug 2024 13:11:26 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , Subject: [PATCH v1 16/16] iommu/arm-smmu-v3: Allow ATS for IOMMU_DOMAIN_NESTED Date: Wed, 7 Aug 2024 13:10:57 -0700 Message-ID: <442b3d5d2b15182f5cc100346183f8c710b7e909.1723061378.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000000A0:EE_|IA1PR12MB6625:EE_ X-MS-Office365-Filtering-Correlation-Id: f6351630-0dae-4498-5ae5-08dcb71d2871 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|376014|7416014|1800799024; X-Microsoft-Antispam-Message-Info: a0lBqDPwfbuVGhoNWwBklzZOK/GRb1n4WsDDDlUqObC4lbm+d+/i7nTkV7rC41g5fM4ghvgyLxSvonlp6KEMNnrEb7o1dyP287TjiBpfOkxiBbEinO6EcAMCSGoWSoTEJmVQBYhxz6zkau0aEWqlJgklos+q70t/g5VBl3xlSbHXpx6GGcdgcA5tEun4ucBG7cSntbPoXW0sTQwT4B2lGlaS/fefIN6KNSRPiWDZLvadEfb0EgbgEfbp6BNp5SjpQcQujAgf7e/74afgSnF475TwhKvqqnfkaTrMc0LAqCse5MP8ejHPRGkMEEGxf+C72klE6pYLCGpRl1ZXn4haGVO0S8YLi1dppjgRacagEtz2XjTufma/lrOihLP2VU2XJJ3S5AIrIA2s33yhNZXtMjFuhWk5/8/xgRiGqv+soUQJC1xWo3xgMpzMvd2nAznOgg5Zfy5Ps/YxB0kuVbk5TYH2dgoy+8yx9xKsyQxcy9N4RZjy9N3zN6C/w4U4rESCB/d30TpzlX7V07z4A92M3aY//PTL11t2DLt5SOOCgmXP6BW9LnRX+Ka1gRUSX7lJwNyX9vTRc/yZ/pyOwfc5pzcg962f6FKeKYUG3BldIsfH9SEiT8mod1/Ch9IJo/OQTZdMSOMdK+S+RqCflAAsa8SNm/AlKY+xfoUsch0oARA+cDxGezJ3pNP5RWjiujaee3E9Du6qZCN299xK5SkaYhLbWmiBQSq4hD7+etDV/xNnIqfvOQSyqcBWIiF/DkWEslgyj2YAqTUzZBk/t49rAERS3Q9aONYmrEILwMRb5B8ZmZZl2MR91kDu10/7reCC96wwqb2xRJwlkPJBu7DOeSs/I9wj/dAN887NHcZ8393deI1mFsW+iMxyELI86YBehS859W58cKP2bpuXAhfZjOg/E1cMyJJfY5yXbXQulUGWscnwarcDWXpKeVS/sAsqxAYvTAh2xF9Z2TTkKW0LRCdCffu2GHmzNW3d5L3LHjxw5oiKdZhXg+7XOUGCNJrK7E7jYCsbj4+P0tVaSjoznMcK/On7MILpIEU+jN7bD+lyKPbckGzeJ1GYGeliPyiIrFlab/NHNkZH2fdcphyO3KGgHMDcsw+nmDlQ99oOmEBdwXZWQZDfnFoVXXT1cLqrIbj4UiPUtv+ZqleWqlObZ+UkRdKZUeqSBeIxMDOnDI/yDTPEqJ3wlZsp8OhWpYRB7W/fF4W6SItalOrseAtK/n9TIMl7TF6YGmAbHNQleS+CmTry2smY+OSZGh1Vp5QCqQeezK0sK8ymNGTOusNnFOizNhjqEsF2RTqLE4RaOtk1pskXUSYdlT8vNs7r5e2sJ8TWq9l+TcHQX4k2vUFknuHIfUwwzmjgKx6NbjbuFEImUw5UjTYg+iVZ/VR1TOdzU5vy72DiEwb4w33CPmJ7RpheYufGNLjBN0qUnhq/zIE3MfsWa/RG1QP25NHaX7kw X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(376014)(7416014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 20:11:43.8657 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6351630-0dae-4498-5ae5-08dcb71d2871 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000000A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6625 From: Jason Gunthorpe Now, ATC invalidation can be done with the VIOMMU invalidation op. A guest owned IOMMU_DOMAIN_NESTED can do an ATS too. Allow it to pass in the EATS field via the vSTE words. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 ++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index be4f849f1a48..ce84f0c04022 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3189,8 +3189,6 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, .master = master, .old_domain = iommu_get_domain_for_dev(dev), .ssid = IOMMU_NO_PASID, - /* Currently invalidation of ATC is not supported */ - .disable_ats = true, }; struct arm_smmu_ste ste; int ret; @@ -3200,6 +3198,15 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, return -EINVAL; mutex_lock(&arm_smmu_asid_lock); + /* + * The VM has to control the actual ATS state at the PCI device because + * we forward the invalidations directly from the VM. If the VM doesn't + * think ATS is on it will not generate ATC flushes and the ATC will + * become incoherent. Since we can't access the actual virtual PCI ATS + * config bit here base this off the EATS value in the STE. If the EATS + * is set then the VM must generate ATC flushes. + */ + state.disable_ats = !nested_domain->enable_ats; ret = arm_smmu_attach_prepare(&state, domain); if (ret) { mutex_unlock(&arm_smmu_asid_lock); @@ -3420,8 +3427,9 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, cfg != STRTAB_STE_0_CFG_S1_TRANS) return ERR_PTR(-EIO); + /* Only Full ATS or ATS UR is supported */ eats = FIELD_GET(STRTAB_STE_1_EATS, le64_to_cpu(arg.ste[1])); - if (eats != STRTAB_STE_1_EATS_ABT) + if (eats != STRTAB_STE_1_EATS_ABT && eats != STRTAB_STE_1_EATS_TRANS) return ERR_PTR(-EIO); if (cfg != STRTAB_STE_0_CFG_S1_TRANS) @@ -3434,6 +3442,7 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, nested_domain->domain.type = IOMMU_DOMAIN_NESTED; nested_domain->domain.ops = &arm_smmu_nested_ops; nested_domain->s2_parent = smmu_parent; + nested_domain->enable_ats = eats == STRTAB_STE_1_EATS_TRANS; nested_domain->ste[0] = arg.ste[0]; nested_domain->ste[1] = arg.ste[1] & ~cpu_to_le64(STRTAB_STE_1_EATS); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index a3fb08e0a195..65f90b00e16d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -811,6 +811,7 @@ struct arm_smmu_domain { struct arm_smmu_nested_domain { struct iommu_domain domain; struct arm_smmu_domain *s2_parent; + u8 enable_ats : 1; __le64 ste[2]; };