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Tue, 27 Aug 2024 10:01:52 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v2 18/19] iommu/arm-smmu-v3: Allow ATS for IOMMU_DOMAIN_NESTED Date: Tue, 27 Aug 2024 09:59:55 -0700 Message-ID: <3962bef2ca6ab9bd06a52910f114345ecfe48ba6.1724776335.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|PH8PR12MB7157:EE_ X-MS-Office365-Filtering-Correlation-Id: 4568eba1-e99d-4799-17b0-08dcc6b9fb20 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: /QVep0xOH2U9v6nvWntIZH/Dt1uDOPFBHeysdcipOyLTrWc1jIIpQJ6WZXi9n+NBE4bbYxMUIiQsZwZjcZvy8t7HQwcjEhoP9gqK2Od2QzkK0RmZ1evu2TpsBqxgw/Z45JHCf3M4OZfEUfGNF81WccNh36tedB6HGs6MXiLlSof+kHLO7HNGLV0Qdlztp85hcafwfXZBNwl7K4EPNCpPZd5vgkLw6uc4r+FfRgjqAurhxFy1dmrpcDLLlL1qHoNVOiJmTHpZT3bfWPOL4JAolUTrScN/ocyqueBDkYuvWnpxCbaP+xDB2klXYby6/1HAlYYbGI9VxwkZAc3JWdyR0IEkoSTBk5Gyay2POwDfTbZaNFxnnqZ/bnkZnsIgzR0fMaIPApaweuN/57IDjU69iMzyQ+NImPOQn0somtCTWGy+bmXSHaGTqISiWywuxAo97cuOwcg01fPIZMhXfq2Kb8tWPaThIqcd3B7B8jEJdMHd0eCyo7oFDY8h5YMkVoYRB2d6sC3wqpJeBlJgF0L9UwRehMqWtUVBcObiDhHaHwZNGS1lyy7rhTRb+G6kpsCutwFDmAYP6ioitZTrZ/xPDQNE8FBVTBgHCh0WRmL/GrN97zky7f6ZOfbGKc5br32JSme37KCkwZ5LXF27/xJC4orHY8f1yVijrz6X9MLc/EuM+OlXTiikOHC5suBieWG3xPorzVTRX6lTj7qxGvlt6WU9E+L982bkS3JxdlrEJ9Ss1aAup0nO4Kmm8D/DGXLxUoWnCQqGiU4wF/2LkCgPU2MmZadbYqwfkw21fNpB6xwQepgZCFJcrqoHopF9oL1eY7z36kklhwtEXrxO0a838DG7kB6m/4MTqw9rYI7G2rD/ZlVPq91eqe+0zvpvJNCmNIGd4EsBNve1x4w+YB32MKt/ZendHdmVosZ31mC+OMjSZRnsdAItl8Y4oemy83HdWIRFV6Yl7eF+FRARLhnelxWNuBGijZ1Kbrw7rptc7if8kWb23FgBRgvMr3jKujlgK2u4oqI1OtLy1TX1H3IJ4Jjg66uMOoIZ0k+2YhFe8xy1V1bU42Mq4Ib+hBRimA0F4+W1grkxc7I2I9prySpbM5FujbtARLZloBRkVWRfQky+6ypbAUIJtP3fJx2HMjstQNEQFJaLDIU0Uxj/68lazJH3QJu9xZykjgbfZcgAua4Kt51WWcLTUqs7xD61yelsUqDrz0LqPNXwiOAv165wByMObQat2Yd8HVmLLzc+97twKCk0JgmWxgDomD60/WIprSxv/eS+2qpMOwpJIEnGtAzkPiIvpPbirzQJaucFohk+XC37spJgmPY+uWQRs/5YK5+4ZFAMDJV5dbNQgiTsAO5LSGbRAFzPf+abK3zoN2RYF9boP/74q3tqWxPZJoRfEpTmSp7zM7ZEpqSohCBFKO7BVyudWcvLiJhy+D4lBHJCODtJMZNEPYZECKjKb1HZ X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2024 17:02:06.3264 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4568eba1-e99d-4799-17b0-08dcc6b9fb20 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7157 From: Jason Gunthorpe Now, ATC invalidation can be done with the VIOMMU invalidation op. A guest owned IOMMU_DOMAIN_NESTED can do an ATS too. Allow it to pass in the EATS field via the vSTE words. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 ++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index bddbb98da414..6627ab87a697 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3237,8 +3237,6 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, .master = master, .old_domain = iommu_get_domain_for_dev(dev), .ssid = IOMMU_NO_PASID, - /* Currently invalidation of ATC is not supported */ - .disable_ats = true, }; struct arm_smmu_ste ste; int ret; @@ -3248,6 +3246,15 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, return -EINVAL; mutex_lock(&arm_smmu_asid_lock); + /* + * The VM has to control the actual ATS state at the PCI device because + * we forward the invalidations directly from the VM. If the VM doesn't + * think ATS is on it will not generate ATC flushes and the ATC will + * become incoherent. Since we can't access the actual virtual PCI ATS + * config bit here base this off the EATS value in the STE. If the EATS + * is set then the VM must generate ATC flushes. + */ + state.disable_ats = !nested_domain->enable_ats; ret = arm_smmu_attach_prepare(&state, domain); if (ret) { mutex_unlock(&arm_smmu_asid_lock); @@ -3497,8 +3504,9 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, cfg != STRTAB_STE_0_CFG_S1_TRANS) return ERR_PTR(-EIO); + /* Only Full ATS or ATS UR is supported */ eats = FIELD_GET(STRTAB_STE_1_EATS, le64_to_cpu(arg.ste[1])); - if (eats != STRTAB_STE_1_EATS_ABT) + if (eats != STRTAB_STE_1_EATS_ABT && eats != STRTAB_STE_1_EATS_TRANS) return ERR_PTR(-EIO); if (cfg != STRTAB_STE_0_CFG_S1_TRANS) @@ -3511,6 +3519,7 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, nested_domain->domain.type = IOMMU_DOMAIN_NESTED; nested_domain->domain.ops = &arm_smmu_nested_ops; nested_domain->s2_parent = smmu_parent; + nested_domain->enable_ats = eats == STRTAB_STE_1_EATS_TRANS; nested_domain->ste[0] = arg.ste[0]; nested_domain->ste[1] = arg.ste[1] & ~cpu_to_le64(STRTAB_STE_1_EATS); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index e7f6e9194a9e..6930810b85cb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -832,6 +832,7 @@ struct arm_smmu_domain { struct arm_smmu_nested_domain { struct iommu_domain domain; struct arm_smmu_domain *s2_parent; + u8 enable_ats : 1; __le64 ste[2]; };