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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B36D.mail.protection.outlook.com (10.167.243.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8398.0 via Frontend Transport; Tue, 28 Jan 2025 12:48:43 +0000 Received: from chalupa-d178host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 28 Jan 2025 06:48:41 -0600 From: Manali Shukla To: , CC: , , , , , , , , , Subject: [PATCH v6 1/3] x86/cpufeatures: Add CPUID feature bit for Idle HLT intercept Date: Tue, 28 Jan 2025 12:48:10 +0000 Message-ID: <20250128124812.7324-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250128124812.7324-1-manali.shukla@amd.com> References: <20250128124812.7324-1-manali.shukla@amd.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B36D:EE_|CY8PR12MB8266:EE_ X-MS-Office365-Filtering-Correlation-Id: 0306e733-2206-4542-eaf6-08dd3f9a1908 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2025 12:48:43.3225 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0306e733-2206-4542-eaf6-08dd3f9a1908 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8266 From: Manali Shukla The Idle HLT Intercept feature allows for the HLT instruction execution by a vCPU to be intercepted by the hypervisor only if there are no pending events (V_INTR and V_NMI) for the vCPU. When the vCPU is expected to service the pending events (V_INTR and V_NMI), the Idle HLT intercept won’t trigger. The feature allows the hypervisor to determine if the vCPU is idle and reduces wasteful VMEXITs. In addition to the aforementioned use case, the Idle HLT intercept feature is also used for enlightened guests who aim to securely manage events without the hypervisor’s awareness. If a HLT occurs while a virtual event is pending and the hypervisor is unaware of this pending event (as could be the case with enlightened guests), the absence of the Idle HLT intercept feature could result in a vCPU being suspended indefinitely. Presence of Idle HLT intercept feature for guests is indicated via CPUID function 0x8000000A_EDX[30]. Signed-off-by: Manali Shukla Acked-by: Borislav Petkov (AMD) --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) base-commit: eb723766b1030a23c38adf2348b7c3d1409d11f0 prerequisite-patch-id: cb345fc0d814a351df2b5788b76eee0eef9de549 prerequisite-patch-id: 71806f400cffe09f47d6231cb072cbdbd540de1b prerequisite-patch-id: 9ea0412aab7ecd8555fcee3e9609dbfe8456d47b prerequisite-patch-id: 3504df50cdd33958456f2e56139d76867273525c prerequisite-patch-id: 674e56729a56cc487cb85be1a64ef561eb7bac8a prerequisite-patch-id: 48e87354f9d6e6bd121ca32ab73cd0d7f1dce74f prerequisite-patch-id: b32c21df6522a7396baa41d62bcad9479041d97a prerequisite-patch-id: 0ff4b504e982db7c1dfa8ec6ac485c92a89f4af8 prerequisite-patch-id: 509018dc2fc1657debc641544e86f5a92d04bc1a diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 645aa360628d..4fef0533f764 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -386,6 +386,7 @@ #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* "v_spec_ctrl" Virtual SPEC_CTRL */ #define X86_FEATURE_VNMI (15*32+25) /* "vnmi" Virtual NMI */ #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* SVME addr check */ +#define X86_FEATURE_IDLE_HLT (15*32+30) /* IDLE HLT intercept */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* "avx512vbmi" AVX512 Vector Bit Manipulation instructions*/