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Sun, 09 Jun 2024 21:45:38 -0700 (PDT) From: Charlie Jenkins Date: Sun, 09 Jun 2024 21:45:07 -0700 Subject: [PATCH 02/13] dt-bindings: thead: add a vlen register length property Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240609-xtheadvector-v1-2-3fe591d7f109@rivosinc.com> References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> In-Reply-To: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1717994732; l=1303; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=kilTkVt6+s7AVwl0Le2KXls/6mRYwW97PnRFwTEsmd0=; b=4RRz7xmpcb7CA1ZMWQZlS9J8l2HdlB2OzfAfqDm1wbd8Q0dPdolWk/sqmZ90bsZ3IlYTtYYew po+8/cap559D5Bi2X+IDlt6JHWqySfqydxCXpaM/iRpkxwpTP5F3ksW X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Add a property analogous to the vlenb CSR so that software can detect the vector length of each CPU prior to it being brought online. Currently software has to assume that the vector length read from the boot CPU applies to all possible CPUs. On T-Head CPUs implementing pre-ratification vector, reading the th.vlenb CSR may produce an illegal instruction trap, so this property is required on such systems. Signed-off-by: Charlie Jenkins --- Documentation/devicetree/bindings/riscv/thead.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml index 301912dcd290..5e578df36ac5 100644 --- a/Documentation/devicetree/bindings/riscv/thead.yaml +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -28,6 +28,13 @@ properties: - const: sipeed,lichee-module-4a - const: thead,th1520 +thead,vlenb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + VLEN/8, the vector register length in bytes. This property is required in + systems where the vector register length is not identical on all harts, or + the vlenb CSR is not available. + additionalProperties: true ...