From patchwork Fri May 3 18:18:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 794692 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2CCC15B969 for ; Fri, 3 May 2024 18:19:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714760355; cv=none; b=ObWthVdS38Wgybis5vABSRYC0DAxFgmSDjsqGdrcp2hVzR9VL1Z1xw8U7dYCIpZVe4YBjDnHkT4RDsQ960KdI3sNIe/lPWgNeBN77hho+VwntPiVk7R9LTrxnzWxnLtosByrhojpDSiV3rNRV57nUWzAWvmtQLJKo0UaotHtjX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714760355; c=relaxed/simple; bh=T4XXjuwF/XccezV6eLQ3i4gZq5aqAqOYHb82qoILg1k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ttCiVIaa224tERRciBFl06YLnmmx/bJt1WJxTmXc0WfMcouGuCSt3rmQ8sBrpkF3Gb5PoahmN5sH58jFcsIZOHE74s7EJKU7/zjHzrwymZhLwvzZfKB/UvLp/75Nj6OR+KZ9me1CvMXfDfRfI5yugyfORpqe2x/yjR5kj/KgTeo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=1YR6Qzcx; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="1YR6Qzcx" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-6f44e3fd382so10731b3a.1 for ; Fri, 03 May 2024 11:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1714760352; x=1715365152; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=B6R6wkBf1KOi3mFl99lu8+x2NZFWF9EQ6yz2lxQorvM=; b=1YR6QzcxMpbkQZ441cW+0I8XBeqqBVyrCLloFAojXDNtvJIqJBKg8zL0ygQUB0xsbl XKwdr9OzsvJptFTbQsDWSUUVaA7QToo/1VNSYJSRIIeTPG7UyPBP2EX9OiJ7m3TtVQJe jviNUEPh4K+QDLQcYA37omAP8f2+6m0iHP/URkhzsbQxZ04UJ3GamNGyivCkbIgBxkDs WHNzkeT3yWRPqxKbUfGLOsV/oyxAkTun29Y33GR44GrSDMwbgMKXseDHBIToet7SSC6d y9A72+WU4W3kQWe13OSmFZFesF5whTjezHUjJMg8VW/t61KetFgrq8eEykor0dJgPmbn wGxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714760352; x=1715365152; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B6R6wkBf1KOi3mFl99lu8+x2NZFWF9EQ6yz2lxQorvM=; b=tTGOEredHEE+djg9GB/07G8xL7bd5OlxirCLwXi/ba2cC5LK88zzlYiHz8FnsOCIQy D2qDN02kzdKxhfSlCJn8gvv9Ka5D+/Aht7/Pi2dSz4NPqrCdhK2GW5SEJqi3nYYWigf2 4xbrsTuFCMd0LRJbAhz4Xn6ZNox1UPKrEVY1PYuoh2VCXl/7V4A97/xuuAG+zY83LDGh Mn+7sIHT3glHcBDvWQGQZpqATmVhTrkQDpVlI9eE8VdRaqanYS3obQgHHUTIgjkLJRep 4sXFXmtIVNTDU64C2sjhxiPWgl83glbP7jh3vsQK04awkzIR/hAytYACpcDp54hbvvMn 210A== X-Forwarded-Encrypted: i=1; AJvYcCWnpEvz1FCUWrxWKtkjKBplziGBXHAc//76n8pj8I+FrQIqIBwAlafdkJ8fNdFgFBQWQsFiWiZSdXfQXRRqeHrD1/dPJzeFMyDd+5dLWS/A X-Gm-Message-State: AOJu0Ywu+R7REyaVUpi5d2+GTazTv2VWywaSxe0PuoYrLvnUQaGvepPI Ls9OjtJ3I0oyvjU1/QUw0EuNdw6kuTOA00TXCRf1NrjsJmmGqPNOEfTOpNF3+/c= X-Google-Smtp-Source: AGHT+IFzyJdNatwMYw5GocFezpafUlJrRNVZEssXp4SJmHftWEiCkeTYkFNtHWaVr1PVwNgggB+ESQ== X-Received: by 2002:a05:6a20:e687:b0:1af:3869:d761 with SMTP id mz7-20020a056a20e68700b001af3869d761mr3824817pzb.3.1714760352171; Fri, 03 May 2024 11:19:12 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id fu6-20020a056a00610600b006f3f5d3595fsm3355421pfb.80.2024.05.03.11.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 11:19:11 -0700 (PDT) From: Charlie Jenkins Date: Fri, 03 May 2024 11:18:29 -0700 Subject: [PATCH v6 14/17] riscv: hwprobe: Add thead vendor extension probing Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240503-dev-charlie-support_thead_vector_6_9-v6-14-cb7624e65d82@rivosinc.com> References: <20240503-dev-charlie-support_thead_vector_6_9-v6-0-cb7624e65d82@rivosinc.com> In-Reply-To: <20240503-dev-charlie-support_thead_vector_6_9-v6-0-cb7624e65d82@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Shuah Khan Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714760319; l=7325; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=T4XXjuwF/XccezV6eLQ3i4gZq5aqAqOYHb82qoILg1k=; b=e8SY5BdNoEb1xlSxBMzjlcui8D/J90bmygArV2ga8OLH2LD57f1TRSVFZdt0uyf9yRTg4UCq8 ahWa34pO1E3DTNGDJ9Oyr3mHSzRnZ8g5bkg4H1OYmT5miuHos5Xxwt5 X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR vendor extension. This new key will allow userspace code to probe for which thead vendor extensions are supported. This API is modeled to be consistent with RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit corresponding to a supported thead vendor extension of the cpumask set. Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program to determine all of the supported thead vendor extensions in one call. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- arch/riscv/include/asm/hwprobe.h | 4 +-- .../include/asm/vendor_extensions/thead_hwprobe.h | 18 +++++++++++ .../include/asm/vendor_extensions/vendor_hwprobe.h | 37 ++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 3 +- arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ arch/riscv/kernel/sys_hwprobe.c | 5 +++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 19 +++++++++++ 8 files changed, 87 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 630507dff5ea..e68496b4f8de 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright 2023 Rivos, Inc + * Copyright 2023-2024 Rivos, Inc */ #ifndef _ASM_HWPROBE_H @@ -8,7 +8,7 @@ #include -#define RISCV_HWPROBE_MAX_KEY 6 +#define RISCV_HWPROBE_MAX_KEY 7 static inline bool riscv_hwprobe_key_is_valid(__s64 key) { diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h new file mode 100644 index 000000000000..925fef39a2c0 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H + +#include + +#include + +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus); +#else +static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) +{ + pair->value = 0; +} +#endif + +#endif diff --git a/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h new file mode 100644 index 000000000000..b6222e7b519e --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2024 Rivos, Inc + */ + +#ifndef _ASM_RISCV_SYS_HWPROBE_H +#define _ASM_RISCV_SYS_HWPROBE_H + +#include + +#define EXT_KEY(ext) \ + do { \ + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \ + pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ + else \ + missing |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ + } while (false) + +/* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + * + * _extension_checks is an arbitrary C block to set the values of pair->value + * and missing. It should be filled with EXT_KEY expressions. + */ +#define VENDOR_EXTENSION_SUPPORTED(pair, cpus, per_hart_thead_bitmap, _extension_checks) \ + do { \ + int cpu; \ + u64 missing; \ + for_each_cpu(cpu, (cpus)) { \ + struct riscv_isavendorinfo *isainfo = &(per_hart_thead_bitmap)[cpu]; \ + _extension_checks \ + } \ + (pair)->value &= ~missing; \ + } while (false) \ + +#endif /* _ASM_RISCV_SYS_HWPROBE_H */ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 9f2a8e3ff204..21e96a63f9ea 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * Copyright 2023 Rivos, Inc + * Copyright 2023-2024 Rivos, Inc */ #ifndef _UAPI_ASM_HWPROBE_H @@ -67,6 +67,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 7 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ /* Flags */ diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/include/uapi/asm/vendor/thead.h new file mode 100644 index 000000000000..43790ebe5faf --- /dev/null +++ b/arch/riscv/include/uapi/asm/vendor/thead.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 8cae41a502dd..aeb70afe230b 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -13,6 +13,7 @@ #include #include #include +#include #include @@ -216,6 +217,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, pair->value = riscv_cboz_block_size; break; + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: + hwprobe_isa_vendor_ext_thead_0(pair, cpus); + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile index 8f1c5a4dc38f..f511fd269e8a 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c new file mode 100644 index 000000000000..53f65942f7e8 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +#include +#include + +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) +{ + VENDOR_EXTENSION_SUPPORTED(pair, cpus, + riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, { + EXT_KEY(XTHEADVECTOR); + }); +}