From patchwork Sun Apr 21 01:04:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 791078 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9F2A14AB2 for ; Sun, 21 Apr 2024 01:04:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713661502; cv=none; b=hOgiIc8YBVJ043/KF3zjAKTA5muKmZQyqE4AXFv/6cD5HTHfmtjv4KP18Ma3K098FgMSK0GPlV6QGDsYRl+G4ujiMFnvPbKZhVXKQQx8A1+2rdwFgP6ywUlWrS6rG6EfFD9NkjigenFhuzdpOyIBYlA/ZqugOCQ0HY2lO/QcxZs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713661502; c=relaxed/simple; bh=VXMH9XTurd5nfcHGFRHuu2Nhe6vpx6wzbqu3UJe1V+c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jKmAJunM/+m6uB3hYZoQF1PqqJun0vzV+o6vtGhzTeRwdwhk/aZclZ5NBGR0Po3Veka3xcxuLZrLAN8B4anqvfh1hTVjQRKvALfNq56ks+KH31cLqn7twQHxhFaxNg60+uu/UZmn3V9I+o8gI/qPD9RhgDZOuNckE7ddPy+bdk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=PaB7tZmH; arc=none smtp.client-ip=209.85.210.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="PaB7tZmH" Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-6edc61d0ff6so3301410b3a.2 for ; Sat, 20 Apr 2024 18:04:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713661499; x=1714266299; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=dB+j6nWh26rIeRnXgCo37eN3ySYMdc7Dea548E01tnE=; b=PaB7tZmHgjkEpnzHBuWAINmjPQKvhgYOUvMcGeYqc1HH3zixrvk3mQJfuLZTPEANYb 66rY9wvpMQFpg+XXuMGOzMEBMsqGGDR4/2QVgx48wGhcAgu9DjWjb9jdWeaxLut3JhIU /XpkYY19P6kZVMF68nfttmsbUPMyDWDUrmnQQtbSdjzsCUtUvOVbL6EXcuw45GTSBFG+ 1NSe5gU/cT05FPfgWzmQFInlBtzHwBfNkSNdTBQtB6Z5K56zPPrh4NoO+XsELmesQkt5 ALSS/l9FnmSsR6o6P8XuRMCuhBnJuS+XoP2Hr4BDbw99nHyIntxbRzyuAhX51tz4sRg6 CcfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713661499; x=1714266299; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dB+j6nWh26rIeRnXgCo37eN3ySYMdc7Dea548E01tnE=; b=C1QjkmELPM6igjul0liLEeLd2mQ8thtN0Viqi1oBVX75CuekySC6Ap425aklLKg5lQ +EQm/Oj/MOKvWM1bjabHUmXjQzZt6TKxnMpGwKbpIHsNTaIwdwJrY/NYw54Y0d0KzFit l0ke+bJ2xTmhz49TtJjkNjiMbCsNQGSacIndfHoKB5JhBwSBiKO1p367FGiuQoGdtnSv Oo5uNksAtYqlof6DGeDNYg/msaQE4n078TI1Yb7Hq/175OQpG1WCDKii6J0NDQakqSX2 4qIHIUg3Ne+zXI4dAlab2WTwj7J9QfI/mSOWGDkFiLt8ud7crnfABOYlFxpqAplok2e7 WIpA== X-Forwarded-Encrypted: i=1; AJvYcCXPCttZePYb+CazbA7jj8YEL5AoZ4hGjVpiI2gHHb7gOBhzlzInp1FqPOUZCQPUOhDj0shMC02dWgO0ZxZOwd8B8xAzGPu+yit7uZCb2Odx X-Gm-Message-State: AOJu0Yz14Fgm26C3UEdwrU6vZmPpT2It6qPd4UQ+9l953HcgrXzIC8hj qnnt9ulDp+GkxpgKy6jlbIv2W7+ELI5piPllH8dFq6q1kBF40f9xRQVziakLLZA= X-Google-Smtp-Source: AGHT+IH7M2YuX2sHdcMrSsjcT8k8DXNsrSO3g+wPSz1mEexn8aNRCjBisKjySDifOvAyqSD7A49evg== X-Received: by 2002:a05:6a00:2da0:b0:6ec:ea4b:f077 with SMTP id fb32-20020a056a002da000b006ecea4bf077mr8615262pfb.16.1713661499094; Sat, 20 Apr 2024 18:04:59 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d6-20020a63d646000000b005dc8702f0a9sm5249627pgj.1.2024.04.20.18.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Apr 2024 18:04:58 -0700 (PDT) From: Charlie Jenkins Date: Sat, 20 Apr 2024 18:04:39 -0700 Subject: [PATCH v3 07/17] riscv: Extend cpufeature.c to detect vendor extensions Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240420-dev-charlie-support_thead_vector_6_9-v3-7-67cff4271d1d@rivosinc.com> References: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com> In-Reply-To: <20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Shuah Khan Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713661481; l=12074; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=VXMH9XTurd5nfcHGFRHuu2Nhe6vpx6wzbqu3UJe1V+c=; b=SqNzWiNSA9eK71TT/KLAa6CI9+oCcYNoa/mQSkzri4iLx2xOAwcFhquxWhZdEUjSseyR0L6Hm tVQnvDtw6vcCIVtEimnC7S9l0iVnVU7z6rObval13LZLL6TDfGAvZaS X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= Separate vendor extensions out into one struct per vendor instead of adding vendor extensions onto riscv_isa_ext. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig | 2 + arch/riscv/Kconfig.vendor | 9 +++ arch/riscv/include/asm/cpufeature.h | 18 ++++++ arch/riscv/include/asm/vendor_extensions.h | 26 ++++++++ arch/riscv/include/asm/vendor_extensions/thead.h | 19 ++++++ arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/cpufeature.c | 75 +++++++++++++++++------- arch/riscv/kernel/vendor_extensions.c | 18 ++++++ arch/riscv/kernel/vendor_extensions/Makefile | 3 + arch/riscv/kernel/vendor_extensions/thead.c | 36 ++++++++++++ 10 files changed, 188 insertions(+), 20 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index be09c8836d56..fec86fba3acd 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -759,6 +759,8 @@ config RISCV_EFFICIENT_UNALIGNED_ACCESS endchoice +source "arch/riscv/Kconfig.vendor" + endmenu # "Platform type" menu "Kernel features" diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor new file mode 100644 index 000000000000..d57254f28ea6 --- /dev/null +++ b/arch/riscv/Kconfig.vendor @@ -0,0 +1,9 @@ +config RISCV_ISA_VENDOR_EXT_THEAD + bool "T-Head vendor extension support" + default y + help + Say N here if you want to disable all T-Head vendor extension + support. This will cause any T-Head vendor extensions that are + requested by hardware probing to be ignored. + + If you don't know what to do here, say Y. diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 809f61ffb667..db6a6d7d6b2e 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -35,6 +35,24 @@ extern u32 riscv_vlenb_dt[NR_CPUS]; void riscv_user_isa_enable(void); +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ + .name = #_name, \ + .property = #_name, \ + .id = _id, \ + .subset_ext_ids = _subset_exts, \ + .subset_ext_size = _subset_exts_size \ +} + +#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) + +/* Used to declare pure "lasso" extension (Zk for instance) */ +#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) + +/* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ +#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) + #if defined(CONFIG_RISCV_MISALIGNED) bool check_unaligned_access_emulated_all_cpus(void); void unaligned_emulation_finish(void); diff --git a/arch/riscv/include/asm/vendor_extensions.h b/arch/riscv/include/asm/vendor_extensions.h new file mode 100644 index 000000000000..0af1ddd0af70 --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2024 Rivos, Inc + */ + +#ifndef _ASM_VENDOR_EXTENSIONS_H +#define _ASM_VENDOR_EXTENSIONS_H + +#include + +#include +#include + +struct riscv_isa_vendor_ext_data_list { + const struct riscv_isa_ext_data *ext_data; + struct riscv_isainfo *per_hart_vendor_bitmap; + unsigned long *vendor_bitmap; + const size_t ext_data_count; + const size_t bitmap_size; +}; + +extern const struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[]; + +extern const size_t riscv_isa_vendor_ext_list_size; + +#endif /* _ASM_VENDOR_EXTENSIONS_H */ diff --git a/arch/riscv/include/asm/vendor_extensions/thead.h b/arch/riscv/include/asm/vendor_extensions/thead.h new file mode 100644 index 000000000000..92eec729888d --- /dev/null +++ b/arch/riscv/include/asm/vendor_extensions/thead.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_H + +#include + +#include + +#define RISCV_ISA_VENDOR_EXT_XTHEADVECTOR 0 + +/* + * Extension keys should be strictly less than max. + * It is safe to increment this when necessary. + */ +#define RISCV_ISA_VENDOR_EXT_MAX_THEAD 32 + +extern const struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead; + +#endif diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 81d94a8ee10f..53361c50fb46 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -58,6 +58,8 @@ obj-y += riscv_ksyms.o obj-y += stacktrace.o obj-y += cacheinfo.o obj-y += patch.o +obj-y += vendor_extensions.o +obj-y += vendor_extensions/ obj-y += probes/ obj-y += tests/ obj-$(CONFIG_MMU) += vdso.o vdso/ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b537731cadef..c9f36822e337 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -24,6 +24,7 @@ #include #include #include +#include #define NUM_ALPHA_EXTS ('z' - 'a' + 1) @@ -102,24 +103,6 @@ static bool riscv_isa_extension_check(int id) return true; } -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \ - .name = #_name, \ - .property = #_name, \ - .id = _id, \ - .subset_ext_ids = _subset_exts, \ - .subset_ext_size = _subset_exts_size \ -} - -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0) - -/* Used to declare pure "lasso" extension (Zk for instance) */ -#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts)) - -/* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */ -#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts)) - static const unsigned int riscv_zk_bundled_exts[] = { RISCV_ISA_EXT_ZBKB, RISCV_ISA_EXT_ZBKC, @@ -353,6 +336,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc bool ext_long = false, ext_err = false; switch (*ext) { + case 'x': + case 'X': + pr_warn("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead."); + /* + * In canonical order, the remaining extensions in the + * isa string will be vendor extensions so exit. + */ + break; case 's': /* * Workaround for invalid single-letter 's' & 'u' (QEMU). @@ -368,8 +359,6 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc } fallthrough; case 'S': - case 'x': - case 'X': case 'z': case 'Z': /* @@ -580,6 +569,48 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) acpi_put_table((struct acpi_table_header *)rhct); } +static void __init riscv_add_cpu_vendor_ext(struct device_node *cpu_node, int cpu) +{ + for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) { + const struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i]; + + for (int j = 0; j < ext_list->ext_data_count; j++) { + const struct riscv_isa_ext_data ext = ext_list->ext_data[j]; + struct riscv_isainfo *isavendorinfo = &ext_list->per_hart_vendor_bitmap[cpu]; + + if (of_property_match_string(cpu_node, "riscv,isa-extensions", + ext.property) < 0) + continue; + + /* + * Assume that subset extensions are all members of the + * same vendor. + */ + if (ext.subset_ext_size) + for (int k = 0; k < ext.subset_ext_size; k++) + set_bit(ext.subset_ext_ids[k], isavendorinfo->isa); + + set_bit(ext.id, isavendorinfo->isa); + } + } +} + +static void __init set_riscv_isa_vendor(int cpu) +{ + for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) { + const struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i]; + + if (bitmap_empty(ext_list->vendor_bitmap, ext_list->bitmap_size)) + bitmap_copy(ext_list->vendor_bitmap, + ext_list->per_hart_vendor_bitmap[cpu].isa, + ext_list->bitmap_size); + else + bitmap_and(ext_list->vendor_bitmap, ext_list->vendor_bitmap, + ext_list->per_hart_vendor_bitmap[cpu].isa, + ext_list->bitmap_size); + } +} + static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) { unsigned int cpu; @@ -623,6 +654,8 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) } } + riscv_add_cpu_vendor_ext(cpu_node, cpu); + of_node_put(cpu_node); /* @@ -638,6 +671,8 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); else bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); + + set_riscv_isa_vendor(cpu); } if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c new file mode 100644 index 000000000000..f76cb3013c2d --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2024 Rivos, Inc + */ + +#include +#include + +#include +#include + +const struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = { +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD + &riscv_isa_vendor_ext_list_thead, +#endif +}; + +const size_t riscv_isa_vendor_ext_list_size = ARRAY_SIZE(riscv_isa_vendor_ext_list); diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile new file mode 100644 index 000000000000..3383066baaab --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o diff --git a/arch/riscv/kernel/vendor_extensions/thead.c b/arch/riscv/kernel/vendor_extensions/thead.c new file mode 100644 index 000000000000..a0a47414ed22 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/thead.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include + +#include +#include + +/* All T-Head vendor extensions supported in Linux */ +const struct riscv_isa_ext_data riscv_isa_vendor_ext_thead[] = { + _RISCV_ISA_EXT_DATA(xtheadvector, RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, NULL, 0), +}; + +/* + * The first member of this struct must be a bitmap named isa so it can be + * compatible with riscv_isainfo even though the sizes of the bitmaps may be + * different. + */ +struct riscv_isavendorinfo_thead { + DECLARE_BITMAP(isa, RISCV_ISA_VENDOR_EXT_MAX_THEAD); +}; + +/* Hart specific T-Head vendor extension support */ +static struct riscv_isavendorinfo_thead hart_vendorinfo_thead[NR_CPUS]; + +/* Set of T-Head vendor extensions supported on all harts */ +DECLARE_BITMAP(vendorinfo_thead, RISCV_ISA_VENDOR_EXT_MAX_THEAD); + +const struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_thead = { + .ext_data = riscv_isa_vendor_ext_thead, + .per_hart_vendor_bitmap = (struct riscv_isainfo *)hart_vendorinfo_thead, + .vendor_bitmap = vendorinfo_thead, + .ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_thead), + .bitmap_size = RISCV_ISA_VENDOR_EXT_MAX_THEAD +};