From patchwork Fri Oct 20 09:24:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yi Liu X-Patchwork-Id: 736484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 254F2C004C0 for ; Fri, 20 Oct 2023 09:24:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376660AbjJTJYd (ORCPT ); Fri, 20 Oct 2023 05:24:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376612AbjJTJYc (ORCPT ); Fri, 20 Oct 2023 05:24:32 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE979D5A; Fri, 20 Oct 2023 02:24:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697793870; x=1729329870; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0njwcX5/NU7naKi/ROVrRqxboo7jMq2jUYAkQziXQWU=; b=J8gfwDbyQTiuY/K2M5/w0CpSDnjcz0yiqW0l8EP2g1IYy+u9y1P3/BzX j0/xONOSh3QLXGpMowV1QFpUJZxGEWqzv3A585t7loG+cALqTETnnqhES yqOFI/OpeRxE/Mh4SXejcnJebFeRtzA3lSGKQXxwF+95Q58Dd225rzjzJ fwDT3noapCkopNSULJsFGWljtj+tYCEfLBd5gQfPqYLmlbDnmlnmHLlrA yHZlUJNIgplJ4RpLsQO/MUbRb06JOv5Kt6PEs3Snl+X5r0jBBsvghFcWS e2s+CP/h/I8mSTaY+DKN96470chootSSm0s3/dfNIYc0qrW5LnPZR2ALS A==; X-IronPort-AV: E=McAfee;i="6600,9927,10868"; a="472685456" X-IronPort-AV: E=Sophos;i="6.03,238,1694761200"; d="scan'208";a="472685456" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2023 02:24:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10868"; a="750859668" X-IronPort-AV: E=Sophos;i="6.03,238,1694761200"; d="scan'208";a="750859668" Received: from 984fee00a4c6.jf.intel.com ([10.165.58.231]) by orsmga007.jf.intel.com with ESMTP; 20 Oct 2023 02:24:28 -0700 From: Yi Liu To: joro@8bytes.org, alex.williamson@redhat.com, jgg@nvidia.com, kevin.tian@intel.com, robin.murphy@arm.com, baolu.lu@linux.intel.com Cc: cohuck@redhat.com, eric.auger@redhat.com, nicolinc@nvidia.com, kvm@vger.kernel.org, mjrosato@linux.ibm.com, chao.p.peng@linux.intel.com, yi.l.liu@intel.com, yi.y.sun@linux.intel.com, peterx@redhat.com, jasowang@redhat.com, shameerali.kolothum.thodi@huawei.com, lulu@redhat.com, suravee.suthikulpanit@amd.com, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, zhenzhong.duan@intel.com, joao.m.martins@oracle.com, xin.zeng@intel.com Subject: [PATCH v5 1/6] iommu: Add cache_invalidate_user op Date: Fri, 20 Oct 2023 02:24:21 -0700 Message-Id: <20231020092426.13907-2-yi.l.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020092426.13907-1-yi.l.liu@intel.com> References: <20231020092426.13907-1-yi.l.liu@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org From: Lu Baolu The updates of the PTEs in the nested page table will be propagated to the hardware caches on both IOMMU (IOTLB) and devices (DevTLB/ATC). Add a new domain op cache_invalidate_user for the userspace to flush the hardware caches for a nested domain through iommufd. No wrapper for it, as it's only supposed to be used by iommufd. Then, pass in invalidation requests in form of a user data array conatining a number of invalidation data entries. Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Signed-off-by: Nicolin Chen Signed-off-by: Yi Liu --- include/linux/iommu.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 48b8a9a03ae7..de52835446f4 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -246,6 +246,24 @@ struct iommu_user_data { size_t len; }; +/** + * struct iommu_user_data_array - iommu driver specific user space data array + * @type: The data type of all the entries in the user buffer array + * @uptr: Pointer to the user buffer array for copy_from_user() + * @entry_len: The fixed-width length of a entry in the array, in bytes + * @entry_num: The number of total entries in the array + * + * A array having a @entry_num number of @entry_len sized entries, each entry is + * user space data, an uAPI defined in include/uapi/linux/iommufd.h where @type + * is also defined as enum iommu_xyz_data_type. + */ +struct iommu_user_data_array { + unsigned int type; + void __user *uptr; + size_t entry_len; + int entry_num; +}; + /** * __iommu_copy_struct_from_user - Copy iommu driver specific user space data * @dst_data: Pointer to an iommu driver specific user data that is defined in @@ -396,6 +414,15 @@ struct iommu_ops { * @iotlb_sync_map: Sync mappings created recently using @map to the hardware * @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush * queue + * @cache_invalidate_user: Flush hardware cache for user space IO page table. + * The @domain must be IOMMU_DOMAIN_NESTED. The @array + * passes in the cache invalidation requests, in form + * of a driver data structure. The driver must update + * array->entry_num to report the number of handled + * invalidation requests. The 32-bit @error_code can + * forward a driver specific error code to user space. + * Both the driver data structure and the error code + * must be defined in include/uapi/linux/iommufd.h * @iova_to_phys: translate iova to physical address * @enforce_cache_coherency: Prevent any kind of DMA from bypassing IOMMU_CACHE, * including no-snoop TLPs on PCIe or other platform @@ -425,6 +452,9 @@ struct iommu_domain_ops { size_t size); void (*iotlb_sync)(struct iommu_domain *domain, struct iommu_iotlb_gather *iotlb_gather); + int (*cache_invalidate_user)(struct iommu_domain *domain, + struct iommu_user_data_array *array, + u32 *error_code); phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova);