From patchwork Fri Feb 25 16:59:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 546006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ABC6C43217 for ; Fri, 25 Feb 2022 17:36:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243808AbiBYRgk (ORCPT ); Fri, 25 Feb 2022 12:36:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243861AbiBYRgh (ORCPT ); Fri, 25 Feb 2022 12:36:37 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D551E1D0D59 for ; Fri, 25 Feb 2022 09:36:04 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 58B8A61DCC for ; Fri, 25 Feb 2022 17:36:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 47A59C36AF8; Fri, 25 Feb 2022 17:36:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1645810563; bh=L0HqwdvbYiaND87l2Hs1ScoOtxDuO+9nPPVblSnqOdY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L7fNn+sKyrFwBvJ9asfJoPYRfRGeB9EsDJUsigZbQYcIoH3nxHNR1ucwjcZBl8Aag hfDUMHb0TC4nhHTRfJijt/ZeYL3SjHmox4HK6EMg5z/FSIOst8w/ya7wUWBAqzYRxu oKY3IhhEL3QCI/PvvSkyXH9UWKxt1e1EmwEPn1AH+lP8JV1MXfiXbXDw1gVgvn952u azLEtHuznnccUKuYARgnoGlNzPVTwzZ88/RMUOcKTwc/dZX9io4ZXenpU2+AUcKUd2 uFXIafd0bS79HYLacogjp+U4BRfQwNu5LgqDRX125ysHy+PkYLVpkxPJn7a2BXt32v xi3DQtDEnS8Bg== From: Mark Brown To: Catalin Marinas , Will Deacon , Marc Zyngier , Shuah Khan , Shuah Khan Cc: Alan Hayward , Luis Machado , Salil Akerkar , Basant Kumar Dwivedi , Szabolcs Nagy , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Mark Brown Subject: [PATCH v12 26/40] KVM: arm64: Hide SME system registers from guests Date: Fri, 25 Feb 2022 16:59:09 +0000 Message-Id: <20220225165923.1474372-27-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220225165923.1474372-1-broonie@kernel.org> References: <20220225165923.1474372-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2636; h=from:subject; bh=L0HqwdvbYiaND87l2Hs1ScoOtxDuO+9nPPVblSnqOdY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiGQreG8ZJ6xoKviHGasD74Yq5je0Pbs1zmr265WxG tQQMVj+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYhkK3gAKCRAk1otyXVSH0Mf7B/ 0dsLWOlFDf6DKmYZHJP3DgfWyDlmPtyRVlkCm7MZYQD4FX3iDe4hJZrQdNqX6wxm+EKFR3SWD3AFCo q7DhmZq3EFxbr5y3bS6aReBfkVz4Q623iEp6oYqagVnyRKUcVpWk0iJcSvisdA/C7Ldy7VgIlqEuZG R9YAD6Aoz4yERz2lAsF1sRSOkup9LMNadf5Uuv3+CH/wYeDRK1xprisORPU5ITCGWODBHxiDDWN3Dn yPkidv4jjEJ3OSZBMRrHEv3zRvQKCgdmA3NJwBQIkIIns798Ylkwu7+IMLjGGLCIQkbZY7uE7BTd/4 CYITkiYVjsf3cYMgx2ydgOBX/VwHJK X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org For the time being we do not support use of SME by KVM guests, support for this will be enabled in future. In order to prevent any side effects or side channels via the new system registers, including the EL0 read/write register TPIDR2, explicitly undefine all the system registers added by SME and mask out the SME bitfield in SYS_ID_AA64PFR1. Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas --- arch/arm64/kvm/sys_regs.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 4dc2fba316ff..43516eda9143 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1089,6 +1089,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, case SYS_ID_AA64PFR1_EL1: if (!kvm_has_mte(vcpu->kvm)) val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE); + + val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_SME); break; case SYS_ID_AA64ISAR1_EL1: if (!vcpu_has_ptrauth(vcpu)) @@ -1508,7 +1510,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), ID_SANITISED(ID_AA64ZFR0_EL1), - ID_UNALLOCATED(4,5), + ID_HIDDEN(ID_AA64SMFR0_EL1), ID_UNALLOCATED(4,6), ID_UNALLOCATED(4,7), @@ -1551,6 +1553,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, { SYS_DESC(SYS_TRFCR_EL1), undef_access }, + { SYS_DESC(SYS_SMPRI_EL1), undef_access }, + { SYS_DESC(SYS_SMCR_EL1), undef_access }, { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, @@ -1633,8 +1637,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, + { SYS_DESC(SYS_SVCR_EL0), undef_access }, { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, .reg = PMCR_EL0 }, @@ -1674,6 +1680,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, + { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },