From patchwork Sat Jul 1 13:42:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Xu X-Patchwork-Id: 698896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4F09EB64DC for ; Sat, 1 Jul 2023 13:37:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229885AbjGANhE (ORCPT ); Sat, 1 Jul 2023 09:37:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229826AbjGANhE (ORCPT ); Sat, 1 Jul 2023 09:37:04 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A41143ABC; Sat, 1 Jul 2023 06:37:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1688218622; x=1719754622; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Dxr6Zdkg56bFHVuAkIb3PHTmV/Q7cAZw8O3SoMXKMZc=; b=KScv6UYTxMS9qqYhMntyckkI9VwolB8mzlk3zb8Oj5ZWbfgQqD5giXhb r/4Kg8TVMHpipuDxbdJd5My+ZKesK3Nv1pOwI9XA2skTNe/VLtoBaCfFW vvmtnwEXmskhWU3//hC2msntbNl4IK0d5w75EryWAUl9+9m+kOyl8Ycl9 q//0CGAu4n5jTKE3hajBFkI21R4TRxzOhH4SELV3TBVF+zmOTIgKwAKtt dep27bdsflpFjKPLxOMfHg1CDPBmRG9IE1u9ZP0WStDCkraGIPL86H1jo yqZxO5FXreDZrPCtLFlmsqifQGzZd/2KGRI5Oa2JK5qdz0JeHKJSVBSy+ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10758"; a="342926027" X-IronPort-AV: E=Sophos;i="6.01,173,1684825200"; d="scan'208";a="342926027" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2023 06:37:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10758"; a="747693831" X-IronPort-AV: E=Sophos;i="6.01,173,1684825200"; d="scan'208";a="747693831" Received: from haibo-optiplex-7090.sh.intel.com ([10.239.159.132]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2023 06:36:54 -0700 From: Haibo Xu Cc: xiaobo55x@gmail.com, haibo1.xu@intel.com, ajones@ventanamicro.com, maz@kernel.org, oliver.upton@linux.dev, seanjc@google.com, Paolo Bonzini , Jonathan Corbet , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Shuah Khan , James Morse , Suzuki K Poulose , Zenghui Yu , Ricardo Koller , Vishal Annapurve , Vipin Sharma , David Matlack , Colton Lewis , kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Subject: [PATCH v5 00/13] RISCV: Add KVM_GET_REG_LIST API Date: Sat, 1 Jul 2023 21:42:48 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org KVM_GET_REG_LIST will dump all register IDs that are available to KVM_GET/SET_ONE_REG and It's very useful to identify some platform regression issue during VM migration. Patch 1-7 re-structured the get-reg-list test in aarch64 to make some of the code as common test framework that can be shared by riscv. Patch 8 move reject_set check logic to a function so as to check for different errno for different registers. Patch 9 move finalize_vcpu back to run_test so that riscv can implement its specific operation. Patch 10 change to do the get/set operation only on present-blessed list. Patch 11 add the skip_set facilities so that riscv can skip set operation on some registers. Patch 12 enabled the KVM_GET_REG_LIST API in riscv. patch 13 added the corresponding kselftest for checking possible register regressions. The get-reg-list kvm selftest was ported from aarch64 and tested with Linux v6.4 on a Qemu riscv64 virt machine. --- Changed since v4: * Rebase to v6.4 * Address Andrew's suggestions and comments: Added skip_set concept Updated errno check logic Modified finalize_vcpu as weak function Andrew Jones (7): KVM: arm64: selftests: Replace str_with_index with strdup_printf KVM: arm64: selftests: Drop SVE cap check in print_reg KVM: arm64: selftests: Remove print_reg's dependency on vcpu_config KVM: arm64: selftests: Rename vcpu_config and add to kvm_util.h KVM: arm64: selftests: Delete core_reg_fixup KVM: arm64: selftests: Split get-reg-list test code KVM: arm64: selftests: Finish generalizing get-reg-list Haibo Xu (6): KVM: arm64: selftests: Move reject_set check logic to a function KVM: arm64: selftests: Move finalize_vcpu back to run_test KVM: selftests: Only do get/set tests on present blessed list KVM: selftests: Add skip_set facility to get_reg_list test KVM: riscv: Add KVM_GET_REG_LIST API support KVM: riscv: selftests: Add get-reg-list test Documentation/virt/kvm/api.rst | 2 +- arch/riscv/kvm/vcpu.c | 375 +++++++++ tools/testing/selftests/kvm/Makefile | 11 +- .../selftests/kvm/aarch64/get-reg-list.c | 544 ++---------- tools/testing/selftests/kvm/get-reg-list.c | 395 +++++++++ .../selftests/kvm/include/kvm_util_base.h | 21 + .../selftests/kvm/include/riscv/processor.h | 3 + .../testing/selftests/kvm/include/test_util.h | 2 + tools/testing/selftests/kvm/lib/test_util.c | 15 + .../selftests/kvm/riscv/get-reg-list.c | 780 ++++++++++++++++++ 10 files changed, 1655 insertions(+), 493 deletions(-) create mode 100644 tools/testing/selftests/kvm/get-reg-list.c create mode 100644 tools/testing/selftests/kvm/riscv/get-reg-list.c