| Message ID | 20240122-arm64-2023-dpisa-v4-0-776e094861df@kernel.org |
|---|---|
| Headers | show |
| Series | arm64: Support for 2023 DPISA extensions | expand |
On Mon, 22 Jan 2024 16:28:06 +0000, Mark Brown <broonie@kernel.org> wrote: > > FEAT_FPMR defines a new EL0 accessible register FPMR use to configure the > FP8 related features added to the architecture at the same time. Detect > support for this register and context switch it for EL0 when present. > > Due to the sharing of responsibility for saving floating point state > between the host kernel and KVM FP8 support is not yet implemented in KVM > and a stub similar to that used for SVCR is provided for FPMR in order to > avoid bisection issues. To make it easier to share host state with the > hypervisor we store FPMR as a hardened usercopy field in uw (along with > some padding). > > Signed-off-by: Mark Brown <broonie@kernel.org> > --- > arch/arm64/include/asm/cpufeature.h | 5 +++++ > arch/arm64/include/asm/fpsimd.h | 2 ++ > arch/arm64/include/asm/kvm_host.h | 1 + > arch/arm64/include/asm/processor.h | 4 ++++ > arch/arm64/kernel/cpufeature.c | 9 +++++++++ > arch/arm64/kernel/fpsimd.c | 13 +++++++++++++ > arch/arm64/kvm/fpsimd.c | 1 + > arch/arm64/tools/cpucaps | 1 + > 8 files changed, 36 insertions(+) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 21c824edf8ce..34fcdbc65d7d 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -768,6 +768,11 @@ static __always_inline bool system_supports_tpidr2(void) > return system_supports_sme(); > } > > +static __always_inline bool system_supports_fpmr(void) > +{ > + return alternative_has_cap_unlikely(ARM64_HAS_FPMR); > +} > + > static __always_inline bool system_supports_cnp(void) > { > return alternative_has_cap_unlikely(ARM64_HAS_CNP); > diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h > index 50e5f25d3024..6cf72b0d2c04 100644 > --- a/arch/arm64/include/asm/fpsimd.h > +++ b/arch/arm64/include/asm/fpsimd.h > @@ -89,6 +89,7 @@ struct cpu_fp_state { > void *sve_state; > void *sme_state; > u64 *svcr; > + unsigned long *fpmr; > unsigned int sve_vl; > unsigned int sme_vl; > enum fp_type *fp_type; > @@ -154,6 +155,7 @@ extern void cpu_enable_sve(const struct arm64_cpu_capabilities *__unused); > extern void cpu_enable_sme(const struct arm64_cpu_capabilities *__unused); > extern void cpu_enable_sme2(const struct arm64_cpu_capabilities *__unused); > extern void cpu_enable_fa64(const struct arm64_cpu_capabilities *__unused); > +extern void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__unused); > > extern u64 read_smcr_features(void); > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 21c57b812569..7993694a54af 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -543,6 +543,7 @@ struct kvm_vcpu_arch { > enum fp_type fp_type; > unsigned int sve_max_vl; > u64 svcr; > + unsigned long fpmr; As this directly represents a register, I'd rather you use a type that represents the size of that register unambiguously (u64). > > /* Stage 2 paging state used by the hardware on next switch */ > struct kvm_s2_mmu *hw_mmu; > diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h > index 5b0a04810b23..b453c66d3fae 100644 > --- a/arch/arm64/include/asm/processor.h > +++ b/arch/arm64/include/asm/processor.h > @@ -155,6 +155,8 @@ struct thread_struct { > struct { > unsigned long tp_value; /* TLS register */ > unsigned long tp2_value; > + unsigned long fpmr; > + unsigned long pad; > struct user_fpsimd_state fpsimd_state; > } uw; > > @@ -253,6 +255,8 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset, > BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) != > sizeof_field(struct thread_struct, uw.tp_value) + > sizeof_field(struct thread_struct, uw.tp2_value) + > + sizeof_field(struct thread_struct, uw.fpmr) + > + sizeof_field(struct thread_struct, uw.pad) + > sizeof_field(struct thread_struct, uw.fpsimd_state)); > > *offset = offsetof(struct thread_struct, uw); > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index eae59ec0f4b0..0263565f617a 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -272,6 +272,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { > }; > > static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), > ARM64_FTR_END, > }; > > @@ -2767,6 +2768,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > .matches = has_lpa2, > }, > + { > + .desc = "FPMR", > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .capability = ARM64_HAS_FPMR, > + .matches = has_cpuid_feature, > + .cpu_enable = cpu_enable_fpmr, > + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) > + }, > {}, > }; > > diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c > index a5dc6f764195..8e24b5e5e192 100644 > --- a/arch/arm64/kernel/fpsimd.c > +++ b/arch/arm64/kernel/fpsimd.c > @@ -359,6 +359,9 @@ static void task_fpsimd_load(void) > WARN_ON(preemptible()); > WARN_ON(test_thread_flag(TIF_KERNEL_FPSTATE)); > > + if (system_supports_fpmr()) > + write_sysreg_s(current->thread.uw.fpmr, SYS_FPMR); > + > if (system_supports_sve() || system_supports_sme()) { > switch (current->thread.fp_type) { > case FP_STATE_FPSIMD: > @@ -446,6 +449,9 @@ static void fpsimd_save_user_state(void) > if (test_thread_flag(TIF_FOREIGN_FPSTATE)) > return; > > + if (system_supports_fpmr()) > + *(last->fpmr) = read_sysreg_s(SYS_FPMR); > + > /* > * If a task is in a syscall the ABI allows us to only > * preserve the state shared with FPSIMD so don't bother > @@ -688,6 +694,12 @@ static void sve_to_fpsimd(struct task_struct *task) > } > } > > +void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__always_unused p) > +{ > + write_sysreg_s(read_sysreg_s(SYS_SCTLR_EL1) | SCTLR_EL1_EnFPM_MASK, > + SYS_SCTLR_EL1); > +} > + > #ifdef CONFIG_ARM64_SVE > /* > * Call __sve_free() directly only if you know task can't be scheduled > @@ -1680,6 +1692,7 @@ static void fpsimd_bind_task_to_cpu(void) > last->sve_vl = task_get_sve_vl(current); > last->sme_vl = task_get_sme_vl(current); > last->svcr = ¤t->thread.svcr; > + last->fpmr = ¤t->thread.uw.fpmr; > last->fp_type = ¤t->thread.fp_type; > last->to_save = FP_STATE_CURRENT; > current->thread.fpsimd_cpu = smp_processor_id(); > diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c > index 8c1d0d4853df..e3e611e30e91 100644 > --- a/arch/arm64/kvm/fpsimd.c > +++ b/arch/arm64/kvm/fpsimd.c > @@ -153,6 +153,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) > fp_state.sve_vl = vcpu->arch.sve_max_vl; > fp_state.sme_state = NULL; > fp_state.svcr = &vcpu->arch.svcr; > + fp_state.fpmr = &vcpu->arch.fpmr; > fp_state.fp_type = &vcpu->arch.fp_type; Given the number of fields you keep track of, it would make a lot more sense if these FP-related fields were in their own little structure and tracked by a single pointer (I don't think there is a case where we track them independently). Thanks, M.
On Mon, 22 Jan 2024 16:28:14 +0000, Mark Brown <broonie@kernel.org> wrote: > > The 2023 architecture extensions have allocated some new ID registers, add > them to the KVM system register descriptions so that they are visible to > guests. > > Signed-off-by: Mark Brown <broonie@kernel.org> > --- > arch/arm64/kvm/sys_regs.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 30253bd19917..38503b1cd2eb 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -2292,12 +2292,12 @@ static const struct sys_reg_desc sys_reg_descs[] = { > ID_AA64PFR0_EL1_AdvSIMD | > ID_AA64PFR0_EL1_FP), }, > ID_SANITISED(ID_AA64PFR1_EL1), > - ID_UNALLOCATED(4,2), > + ID_SANITISED(ID_AA64PFR2_EL1), So you now expose all sort of MTE things to the guest? > ID_UNALLOCATED(4,3), > ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), > ID_HIDDEN(ID_AA64SMFR0_EL1), > ID_UNALLOCATED(4,6), > - ID_UNALLOCATED(4,7), > + ID_SANITISED(ID_AA64FPFR0_EL1), > > /* CRm=5 */ > { SYS_DESC(SYS_ID_AA64DFR0_EL1), > @@ -2324,7 +2324,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { > ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | > ID_AA64ISAR2_EL1_APA3 | > ID_AA64ISAR2_EL1_GPA3)), > - ID_UNALLOCATED(6,3), > + ID_WRITABLE(ID_AA64ISAR3_EL1, ~ID_AA64ISAR3_EL1_RES0), How about the non dpISA stuff that is advertised in the same register, and for which no support exists? > ID_UNALLOCATED(6,4), > ID_UNALLOCATED(6,5), > ID_UNALLOCATED(6,6), > M.
This series enables support for the data processing extensions in the newly released 2023 architecture, this is mainly support for 8 bit floating point formats. Most of the extensions only introduce new instructions and therefore only require hwcaps but there is a new EL0 visible control register FPMR used to control the 8 bit floating point formats, we need to manage traps for this and context switch it. Due to uncertainty with the plan for parsing ID registers to identify which features to expose to the guest the KVM support is placed at the end of the series, it will need to be revised once that issue is resolved. The sharing of floating point save code between the host and guest kernels slightly complicates the introduction of KVM support, we first introduce host support with some placeholders for KVM then replace those with the actual KVM support. I've not added test coverage for ptrace, I've got a test program which exercises all the FP ptrace interfaces and their interactions together, my plan is to cover it there rather than add another tiny test program that duplicates the boilerplace for tracing a target and doesn't actually run the traced program. Signed-off-by: Mark Brown <broonie@kernel.org> --- Changes in v4: - Rebase onto v6.8-rc1. - Move KVM support to the end of the series. - Link to v3: https://lore.kernel.org/r/20231205-arm64-2023-dpisa-v3-0-dbcbcd867a7f@kernel.org Changes in v3: - Rebase onto v6.7-rc3. - Hook up traps for FPMR in emulate-nested.c. - Link to v2: https://lore.kernel.org/r/20231114-arm64-2023-dpisa-v2-0-47251894f6a8@kernel.org Changes in v2: - Rebase onto v6.7-rc1. - Link to v1: https://lore.kernel.org/r/20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org --- Mark Brown (14): arm64/cpufeature: Hook new identification registers up to cpufeature arm64/fpsimd: Enable host kernel access to FPMR arm64/fpsimd: Support FEAT_FPMR arm64/signal: Add FPMR signal handling arm64/ptrace: Expose FPMR via ptrace arm64/hwcap: Define hwcaps for 2023 DPISA features kselftest/arm64: Handle FPMR context in generic signal frame parser kselftest/arm64: Add basic FPMR test kselftest/arm64: Add 2023 DPISA hwcap test coverage KVM: arm64: Share all userspace hardened thread data with the hypervisor KVM: arm64: Add newly allocated ID registers to register descriptions KVM: arm64: Support FEAT_FPMR for guests KVM: arm64: selftests: Document feature registers added in 2023 extensions KVM: arm64: selftests: Teach get-reg-list about FPMR Documentation/arch/arm64/elf_hwcaps.rst | 49 +++++ arch/arm64/include/asm/cpu.h | 3 + arch/arm64/include/asm/cpufeature.h | 5 + arch/arm64/include/asm/fpsimd.h | 2 + arch/arm64/include/asm/hwcap.h | 15 ++ arch/arm64/include/asm/kvm_arm.h | 4 +- arch/arm64/include/asm/kvm_host.h | 5 +- arch/arm64/include/asm/processor.h | 6 +- arch/arm64/include/uapi/asm/hwcap.h | 15 ++ arch/arm64/include/uapi/asm/sigcontext.h | 8 + arch/arm64/kernel/cpufeature.c | 72 +++++++ arch/arm64/kernel/cpuinfo.c | 18 ++ arch/arm64/kernel/fpsimd.c | 13 ++ arch/arm64/kernel/ptrace.c | 42 ++++ arch/arm64/kernel/signal.c | 59 ++++++ arch/arm64/kvm/emulate-nested.c | 8 + arch/arm64/kvm/fpsimd.c | 14 +- arch/arm64/kvm/hyp/include/hyp/switch.h | 9 +- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 4 +- arch/arm64/kvm/sys_regs.c | 17 +- arch/arm64/tools/cpucaps | 1 + include/uapi/linux/elf.h | 1 + tools/testing/selftests/arm64/abi/hwcap.c | 217 +++++++++++++++++++++ tools/testing/selftests/arm64/signal/.gitignore | 1 + .../arm64/signal/testcases/fpmr_siginfo.c | 82 ++++++++ .../selftests/arm64/signal/testcases/testcases.c | 8 + .../selftests/arm64/signal/testcases/testcases.h | 1 + tools/testing/selftests/kvm/aarch64/get-reg-list.c | 11 +- 28 files changed, 670 insertions(+), 20 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20231003-arm64-2023-dpisa-2f3d25746474 Best regards,