From patchwork Tue Jan 9 08:40:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Makhalov X-Patchwork-Id: 761297 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D027C38DDB for ; Tue, 9 Jan 2024 08:41:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="d5lMnuwk" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-6daa89a6452so1468529b3a.2 for ; Tue, 09 Jan 2024 00:41:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1704789678; x=1705394478; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HeZ7Yc/QAQMqHdvRNSeL3MLzDzQAumC8yqHea160CSY=; b=d5lMnuwkPYtFwt9V3EurtqkaHaeRVMcXG9Y96ybFJ5SouEnCo2kepx9FkpgUv51S+o cifzO1eNoGAErRguitjRMTad/XHH93kN5ScsMyrnUV89x1J/aA83RS5IF5O8UZtv9AbD LQzw7X9bedcsDWdi82Nzsk9U9TgwxNrs/IGBw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704789678; x=1705394478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HeZ7Yc/QAQMqHdvRNSeL3MLzDzQAumC8yqHea160CSY=; b=KaJEsuRpker0Z5WJprrF+WCwq4jtTaiFrWOHEey1huD1j4ycs+7uQwZ7Iht3DYp7RK 8PedB9YqeDAOlt3YdGN1mVOQ2wHLUsvbVxu5OAz7IX8/qUOH3ibOmygvOOcTtOlEs9YX 4/RPL0hbgtSN1ptYkV6vYC4xVopX5Auv+l7Tm5K2nBtALBYWsIMa0Cu9Jp3ND3DK2kiV IB7/PvkoXsZArDMxc+igC5af2mb0CydwprgR4avup6xLoLXvFrHYk/MT+KgNVmnJi3p5 5LL/r5etUyv7I9yGMmbjb6TcGzC1/yx9JbJeVCAh7vzqB3hQ6JHf5DZ4rryklFIwjq1e tcxw== X-Gm-Message-State: AOJu0YzCIZ9rD6zgPGIaEWlLR+aXV1zwalZ9dHu4crTzR2LgRhW5LsBq EvOBkZWInSvoTs8eBZpRCFrdBT6hr1qa X-Google-Smtp-Source: AGHT+IFxx53kVarjHq5z7rzVIUwCkyk+NGFUSVTP7cmO2YtnOt1zBEsFEwgvVWBZJ0j2JxOYS0P1zg== X-Received: by 2002:a05:6a21:8187:b0:199:bb69:a6ed with SMTP id pd7-20020a056a21818700b00199bb69a6edmr1524423pzb.114.1704789678164; Tue, 09 Jan 2024 00:41:18 -0800 (PST) Received: from amakhalov-build-vm.eng.vmware.com ([128.177.82.146]) by smtp.gmail.com with ESMTPSA id sf15-20020a17090b51cf00b0028d435cc2cbsm4772293pjb.15.2024.01.09.00.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jan 2024 00:41:17 -0800 (PST) From: Alexey Makhalov X-Google-Original-From: Alexey Makhalov To: linux-kernel@vger.kernel.org, virtualization@lists.linux.dev, bp@alien8.de, hpa@zytor.com, dave.hansen@linux.intel.com, mingo@redhat.com, tglx@linutronix.de Cc: x86@kernel.org, netdev@vger.kernel.org, richardcochran@gmail.com, linux-input@vger.kernel.org, dmitry.torokhov@gmail.com, zackr@vmware.com, linux-graphics-maintainer@vmware.com, pv-drivers@vmware.com, namit@vmware.com, timothym@vmware.com, akaher@vmware.com, jsipek@vmware.com, dri-devel@lists.freedesktop.org, daniel@ffwll.ch, airlied@gmail.com, tzimmermann@suse.de, mripard@kernel.org, maarten.lankhorst@linux.intel.com, horms@kernel.org, kirill.shutemov@linux.intel.com Subject: [PATCH v6 7/7] x86/vmware: Add TDX hypercall support Date: Tue, 9 Jan 2024 00:40:52 -0800 Message-Id: <20240109084052.58661-8-amakhalov@vmware.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20240109084052.58661-1-amakhalov@vmware.com> References: <20240109084052.58661-1-amakhalov@vmware.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 VMware hypercalls use I/O port, VMCALL or VMMCALL instructions. Add __tdx_hypercall path to support TDX guests. No change in high bandwidth hypercalls, as only low bandwidth ones are supported for TDX guests. Co-developed-by: Tim Merrifield Signed-off-by: Tim Merrifield Signed-off-by: Alexey Makhalov Reviewed-by: Nadav Amit Acked-by: Kirill A. Shutemov Acked-by: Dave Hansen --- arch/x86/include/asm/vmware.h | 79 +++++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/vmware.c | 25 +++++++++++ 2 files changed, 104 insertions(+) diff --git a/arch/x86/include/asm/vmware.h b/arch/x86/include/asm/vmware.h index 84a31f579a30..3bd593c6591d 100644 --- a/arch/x86/include/asm/vmware.h +++ b/arch/x86/include/asm/vmware.h @@ -18,6 +18,12 @@ * arg2 - Hypercall command * arg3 bits [15:0] - Port number, LB and direction flags * + * - Low bandwidth TDX hypercalls (x86_64 only) are similar to LB + * hypercalls. They also have up to 6 input and 6 output on registers + * arguments, with different argument to register mapping: + * %r12 (arg0), %rbx (arg1), %r13 (arg2), %rdx (arg3), + * %rsi (arg4), %rdi (arg5). + * * - High bandwidth (HB) hypercalls are I/O port based only. They have * up to 7 input and 7 output arguments passed and returned using * registers: %eax (arg0), %ebx (arg1), %ecx (arg2), %edx (arg3), @@ -54,12 +60,61 @@ #define VMWARE_CMD_GETHZ 45 #define VMWARE_CMD_GETVCPU_INFO 68 #define VMWARE_CMD_STEALCLOCK 91 +/* + * Hypercall command mask: + * bits [6:0] command, range [0, 127] + * bits [19:16] sub-command, range [0, 15] + */ +#define VMWARE_CMD_MASK 0xf007fU #define CPUID_VMWARE_FEATURES_ECX_VMMCALL BIT(0) #define CPUID_VMWARE_FEATURES_ECX_VMCALL BIT(1) extern u8 vmware_hypercall_mode; +#define VMWARE_TDX_VENDOR_LEAF 0x1af7e4909ULL +#define VMWARE_TDX_HCALL_FUNC 1 + +extern unsigned long vmware_tdx_hypercall(unsigned long cmd, + struct tdx_module_args *args); + +/* + * TDCALL[TDG.VP.VMCALL] uses %rax (arg0) and %rcx (arg2). Therefore, + * we remap those registers to %r12 and %r13, respectively. + */ +static inline +unsigned long vmware_tdx_hypercall_args(unsigned long cmd, unsigned long in1, + unsigned long in3, unsigned long in4, + unsigned long in5, + uint32_t *out1, uint32_t *out2, + uint32_t *out3, uint32_t *out4, + uint32_t *out5) +{ + unsigned long ret; + + struct tdx_module_args args = { + .rbx = in1, + .rdx = in3, + .rsi = in4, + .rdi = in5, + }; + + ret = vmware_tdx_hypercall(cmd, &args); + + if (out1) + *out1 = args.rbx; + if (out2) + *out2 = args.r13; + if (out3) + *out3 = args.rdx; + if (out4) + *out4 = args.rsi; + if (out5) + *out5 = args.rdi; + + return ret; +} + /* * The low bandwidth call. The low word of %edx is presumed to have OUT bit * set. The high word of %edx may contain input data from the caller. @@ -87,6 +142,10 @@ unsigned long vmware_hypercall1(unsigned long cmd, unsigned long in1) { unsigned long out0; + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return vmware_tdx_hypercall_args(cmd, in1, 0, 0, 0, + NULL, NULL, NULL, NULL, NULL); + asm_inline volatile (VMWARE_HYPERCALL : "=a" (out0) : [port] "i" (VMWARE_HYPERVISOR_PORT), @@ -105,6 +164,10 @@ unsigned long vmware_hypercall3(unsigned long cmd, unsigned long in1, { unsigned long out0; + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return vmware_tdx_hypercall_args(cmd, in1, 0, 0, 0, + out1, out2, NULL, NULL, NULL); + asm_inline volatile (VMWARE_HYPERCALL : "=a" (out0), "=b" (*out1), "=c" (*out2) : [port] "i" (VMWARE_HYPERVISOR_PORT), @@ -124,6 +187,10 @@ unsigned long vmware_hypercall4(unsigned long cmd, unsigned long in1, { unsigned long out0; + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return vmware_tdx_hypercall_args(cmd, in1, 0, 0, 0, + out1, out2, out3, NULL, NULL); + asm_inline volatile (VMWARE_HYPERCALL : "=a" (out0), "=b" (*out1), "=c" (*out2), "=d" (*out3) : [port] "i" (VMWARE_HYPERVISOR_PORT), @@ -143,6 +210,10 @@ unsigned long vmware_hypercall5(unsigned long cmd, unsigned long in1, { unsigned long out0; + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return vmware_tdx_hypercall_args(cmd, in1, in3, in4, in5, + NULL, out2, NULL, NULL, NULL); + asm_inline volatile (VMWARE_HYPERCALL : "=a" (out0), "=c" (*out2) : [port] "i" (VMWARE_HYPERVISOR_PORT), @@ -165,6 +236,10 @@ unsigned long vmware_hypercall6(unsigned long cmd, unsigned long in1, { unsigned long out0; + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return vmware_tdx_hypercall_args(cmd, in1, in3, 0, 0, + NULL, out2, out3, out4, out5); + asm_inline volatile (VMWARE_HYPERCALL : "=a" (out0), "=c" (*out2), "=d" (*out3), "=S" (*out4), "=D" (*out5) @@ -186,6 +261,10 @@ unsigned long vmware_hypercall7(unsigned long cmd, unsigned long in1, { unsigned long out0; + if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return vmware_tdx_hypercall_args(cmd, in1, in3, in4, in5, + out1, out2, out3, NULL, NULL); + asm_inline volatile (VMWARE_HYPERCALL : "=a" (out0), "=b" (*out1), "=c" (*out2), "=d" (*out3) : [port] "i" (VMWARE_HYPERVISOR_PORT), diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index 3aa1adaed18f..84caa67d4820 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -428,6 +428,31 @@ static bool __init vmware_legacy_x2apic_available(void) (eax & BIT(VCPU_LEGACY_X2APIC)); } +#ifdef CONFIG_INTEL_TDX_GUEST +unsigned long vmware_tdx_hypercall(unsigned long cmd, + struct tdx_module_args *args) +{ + if (!hypervisor_is_type(X86_HYPER_VMWARE)) + return ULONG_MAX; + + if (cmd & ~VMWARE_CMD_MASK) { + pr_warn_once("Out of range command %lx\n", cmd); + return ULONG_MAX; + } + + args->r10 = VMWARE_TDX_VENDOR_LEAF; + args->r11 = VMWARE_TDX_HCALL_FUNC; + args->r12 = VMWARE_HYPERVISOR_MAGIC; + args->r13 = cmd; + args->r15 = 0; /* CPL */ + + __tdx_hypercall(args); + + return args->r12; +} +EXPORT_SYMBOL_GPL(vmware_tdx_hypercall); +#endif + #ifdef CONFIG_AMD_MEM_ENCRYPT static void vmware_sev_es_hcall_prepare(struct ghcb *ghcb, struct pt_regs *regs)