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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A0.mail.protection.outlook.com (10.167.242.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Fri, 17 Nov 2023 08:11:52 +0000 Received: from jatayu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 17 Nov 2023 02:11:48 -0600 From: Shyam Sundar S K To: , , , , , CC: , , , , "Shyam Sundar S K" Subject: [PATCH v5 13/17] platform/x86/amd/pmf: Add PMF-AMDGPU get interface Date: Fri, 17 Nov 2023 13:37:43 +0530 Message-ID: <20231117080747.3643990-14-Shyam-sundar.S-k@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231117080747.3643990-1-Shyam-sundar.S-k@amd.com> References: <20231117080747.3643990-1-Shyam-sundar.S-k@amd.com> Precedence: bulk X-Mailing-List: linux-input@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A0:EE_|DS7PR12MB5717:EE_ X-MS-Office365-Filtering-Correlation-Id: 74380d76-9b90-4a93-9584-08dbe744db0d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2023 08:11:52.1325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74380d76-9b90-4a93-9584-08dbe744db0d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5717 In order to provide GPU inputs to TA for the Smart PC solution to work, we need to have interface between the PMF driver and the AMDGPU driver. Add the initial code path for get interface from AMDGPU. Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello Signed-off-by: Shyam Sundar S K --- drivers/platform/x86/amd/pmf/core.c | 3 +- drivers/platform/x86/amd/pmf/pmf.h | 18 +++++++ drivers/platform/x86/amd/pmf/spc.c | 41 ++++++++++++++ drivers/platform/x86/amd/pmf/tee-if.c | 77 +++++++++++++++++++++++++++ 4 files changed, 138 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/amd/pmf/core.c b/drivers/platform/x86/amd/pmf/core.c index 4b8156033fa6..9b14a997cd48 100644 --- a/drivers/platform/x86/amd/pmf/core.c +++ b/drivers/platform/x86/amd/pmf/core.c @@ -411,6 +411,7 @@ static int amd_pmf_probe(struct platform_device *pdev) } dev->cpu_id = rdev->device; + dev->root = rdev; err = amd_smn_read(0, AMD_PMF_BASE_ADDR_LO, &val); if (err) { @@ -482,4 +483,4 @@ module_platform_driver(amd_pmf_driver); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("AMD Platform Management Framework Driver"); -MODULE_SOFTDEP("pre: amdtee"); +MODULE_SOFTDEP("pre: amdtee amdgpu"); diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h index 8712299ad52b..525308519fa3 100644 --- a/drivers/platform/x86/amd/pmf/pmf.h +++ b/drivers/platform/x86/amd/pmf/pmf.h @@ -11,7 +11,11 @@ #ifndef PMF_H #define PMF_H +#include +#include #include +#include +#include #include #define POLICY_BUF_MAX_SZ 0x4b000 @@ -83,6 +87,8 @@ #define TA_OUTPUT_RESERVED_MEM 906 #define MAX_OPERATION_PARAMS 4 +#define MAX_SUPPORTED_DISPLAY 4 + /* AMD PMF BIOS interfaces */ struct apmf_verify_interface { u16 size; @@ -194,6 +200,15 @@ enum power_modes { POWER_MODE_MAX, }; +struct amd_gpu_pmf_data { + struct pci_dev *gpu_dev; + struct backlight_device *raw_bd; + struct thermal_cooling_device *cooling_dev; + enum drm_connector_status con_status[MAX_SUPPORTED_DISPLAY]; + int display_count; + int connector_type[MAX_SUPPORTED_DISPLAY]; +}; + struct amd_pmf_dev { void __iomem *regbase; void __iomem *smu_virt_addr; @@ -228,9 +243,12 @@ struct amd_pmf_dev { void *shbuf; struct delayed_work pb_work; struct pmf_action_table *prev_data; + struct amd_gpu_pmf_data gfx_data; u64 policy_addr; void *policy_base; bool smart_pc_enabled; + struct pci_dev *root; + struct drm_device *drm_dev; }; struct apmf_sps_prop_granular { diff --git a/drivers/platform/x86/amd/pmf/spc.c b/drivers/platform/x86/amd/pmf/spc.c index 959146fd483f..47ec563088b8 100644 --- a/drivers/platform/x86/amd/pmf/spc.c +++ b/drivers/platform/x86/amd/pmf/spc.c @@ -44,6 +44,10 @@ void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table * dev_dbg(dev->dev, "Max C0 Residency: %u\n", in->ev_info.max_c0residency); dev_dbg(dev->dev, "GFX Busy: %u\n", in->ev_info.gfx_busy); dev_dbg(dev->dev, "Connected Display Count: %u\n", in->ev_info.monitor_count); + dev_dbg(dev->dev, "Primary Display Type: %s\n", + drm_get_connector_type_name(in->ev_info.display_type)); + dev_dbg(dev->dev, "Primary Display State: %s\n", in->ev_info.display_state ? + "Connected" : "disconnected/unknown"); dev_dbg(dev->dev, "LID State: %s\n", in->ev_info.lid_state ? "close" : "open"); dev_dbg(dev->dev, "==== TA inputs END ====\n"); } @@ -146,6 +150,41 @@ static int amd_pmf_get_slider_info(struct amd_pmf_dev *dev, struct ta_pmf_enact_ return 0; } +static int amd_pmf_get_gfx_data(struct amd_pmf_dev *pmf) +{ + struct drm_connector_list_iter iter; + struct drm_connector *connector; + int i = 0; + + /* Reset the count to zero */ + pmf->gfx_data.display_count = 0; + + drm_connector_list_iter_begin(pmf->drm_dev, &iter); + drm_for_each_connector_iter(connector, &iter) { + if (connector->status == connector_status_connected) + pmf->gfx_data.display_count++; + if (connector->status != pmf->gfx_data.con_status[i]) + pmf->gfx_data.con_status[i] = connector->status; + if (connector->connector_type != pmf->gfx_data.connector_type[i]) + pmf->gfx_data.connector_type[i] = connector->connector_type; + + i++; + if (i >= MAX_SUPPORTED_DISPLAY) + break; + } + drm_connector_list_iter_end(&iter); + + return 0; +} + +static void amd_pmf_get_gpu_info(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) +{ + amd_pmf_get_gfx_data(dev); + in->ev_info.monitor_count = dev->gfx_data.display_count; + in->ev_info.display_type = dev->gfx_data.connector_type[0]; + in->ev_info.display_state = dev->gfx_data.con_status[0]; +} + void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in) { /* TA side lid open is 1 and close is 0, hence the ! here */ @@ -154,4 +193,6 @@ void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_tab amd_pmf_get_smu_info(dev, in); amd_pmf_get_battery_info(dev, in); amd_pmf_get_slider_info(dev, in); + if (dev->drm_dev) + amd_pmf_get_gpu_info(dev, in); } diff --git a/drivers/platform/x86/amd/pmf/tee-if.c b/drivers/platform/x86/amd/pmf/tee-if.c index 81b1bd356e83..82ee2b1c627f 100644 --- a/drivers/platform/x86/amd/pmf/tee-if.c +++ b/drivers/platform/x86/amd/pmf/tee-if.c @@ -10,6 +10,7 @@ #include #include +#include #include #include "pmf.h" @@ -422,6 +423,60 @@ static void amd_pmf_tee_deinit(struct amd_pmf_dev *dev) tee_client_close_context(dev->tee_ctx); } +static int amd_pmf_gpu_get_cur_state(struct thermal_cooling_device *cooling_dev, + unsigned long *state) +{ + struct backlight_device *bd; + + if (acpi_video_get_backlight_type() != acpi_backlight_native) + return -ENODEV; + + bd = backlight_device_get_by_type(BACKLIGHT_RAW); + if (!bd) + return -ENODEV; + + *state = backlight_get_brightness(bd); + + return 0; +} + +static int amd_pmf_gpu_get_max_state(struct thermal_cooling_device *cooling_dev, + unsigned long *state) +{ + struct backlight_device *bd; + + if (acpi_video_get_backlight_type() != acpi_backlight_native) + return -ENODEV; + + bd = backlight_device_get_by_type(BACKLIGHT_RAW); + if (!bd) + return -ENODEV; + + if (backlight_is_blank(bd)) + *state = 0; + else + *state = bd->props.max_brightness; + + return 0; +} + +static const struct thermal_cooling_device_ops bd_cooling_ops = { + .get_max_state = amd_pmf_gpu_get_max_state, + .get_cur_state = amd_pmf_gpu_get_cur_state, +}; + +static int amd_pmf_get_gpu_handle(struct pci_dev *pdev, void *data) +{ + struct amd_pmf_dev *dev = data; + + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->devfn == 0) { + dev->gfx_data.gpu_dev = pdev; + return 1; /* Stop walking */ + } + + return 0; /* Continue walking */ +} + int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev) { int ret; @@ -433,10 +488,30 @@ int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev) INIT_DELAYED_WORK(&dev->pb_work, amd_pmf_invoke_cmd); amd_pmf_set_dram_addr(dev); amd_pmf_get_bios_buffer(dev); + dev->prev_data = kzalloc(sizeof(*dev->prev_data), GFP_KERNEL); if (!dev->prev_data) return -ENOMEM; + pci_walk_bus(dev->root->bus, amd_pmf_get_gpu_handle, dev); + if (dev->gfx_data.gpu_dev) { + dev->drm_dev = pci_get_drvdata(dev->gfx_data.gpu_dev); + if (!dev->drm_dev) + return -EINVAL; + + if (acpi_video_get_backlight_type() != acpi_backlight_native) + return -ENODEV; + + dev->gfx_data.raw_bd = backlight_device_get_by_type(BACKLIGHT_RAW); + if (!dev->gfx_data.raw_bd) + return -ENODEV; + + dev->gfx_data.cooling_dev = thermal_cooling_device_register("pmf_gpu_bd", + NULL, &bd_cooling_ops); + if (IS_ERR(dev->gfx_data.cooling_dev)) + return -ENODEV; + } + return dev->smart_pc_enabled; } @@ -448,5 +523,7 @@ void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev) kfree(dev->prev_data); kfree(dev->policy_buf); cancel_delayed_work_sync(&dev->pb_work); + if (dev->gfx_data.cooling_dev) + thermal_cooling_device_unregister(dev->gfx_data.cooling_dev); amd_pmf_tee_deinit(dev); }