From patchwork Wed Oct 28 22:54:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Khalil Blaiech X-Patchwork-Id: 310920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CE2AC388F7 for ; Wed, 28 Oct 2020 22:55:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D6B320756 for ; Wed, 28 Oct 2020 22:55:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="D1oASc0m" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389779AbgJ1WzF (ORCPT ); Wed, 28 Oct 2020 18:55:05 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:16502 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389776AbgJ1WzF (ORCPT ); Wed, 28 Oct 2020 18:55:05 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 28 Oct 2020 15:55:08 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 28 Oct 2020 22:55:04 +0000 Received: from vdi.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 28 Oct 2020 22:55:04 +0000 From: Khalil Blaiech To: CC: , , Leon Romanovsky Subject: [PATCH i2c-next v1 4/6] i2c: mlxbf: Update reference clock frequency Date: Wed, 28 Oct 2020 18:54:20 -0400 Message-ID: X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603925708; bh=JGOozmSPHS6vJ6hfE4OWIInXIDFQZ962Oubpd+qGEHk=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:Content-Type; b=D1oASc0mvB/4Bv8Q6RNHXB04nscQa3kv3zuNl4uCucVPur61zD0jzAP4HCC1GxKYx 0Sgsw7sMHYAAl0hWkEv5IF2hXOav3/MuRi7rNY4/fv0OG+g6gAeEAKBg8oxf0pEsOO +cZrZmVXZ0x4f6+/WAOor3sCTAJo9sEh2NklhAy2JdkQRUMTgQuETaNF9TYgRLpfI5 s+t+zeft8lYuY7aMHJLTE10w+qtd9T9/0CnBuc8BCdIHKantId5+LlZO5nZvl3/AkX +rubMNH2F7R6e8QrcLkkaWqDwouiwcLTKF3eE3rd5+K1BiniCX8g7CoZSSygVSq7IE p/PQoSi+ddPZQ== Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org The reference clock frequency remains the same across Bluefield products. Thus, update the frequency and rename the macro. Fixes: b5b5b32081cd206b ("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC") Reviewed-by: Leon Romanovsky Signed-off-by: Khalil Blaiech --- drivers/i2c/busses/i2c-mlxbf.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-mlxbf.c b/drivers/i2c/busses/i2c-mlxbf.c index fca8a3bddcb1..afc996d07504 100644 --- a/drivers/i2c/busses/i2c-mlxbf.c +++ b/drivers/i2c/busses/i2c-mlxbf.c @@ -62,10 +62,8 @@ * Master. Default value is set to 400MHz. */ #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) -/* Reference clock for Bluefield 1 - 156 MHz. */ -#define MLXBF_I2C_TYU_PLL_IN_FREQ (156 * 1000 * 1000) -/* Reference clock for BlueField 2 - 200 MHz. */ -#define MLXBF_I2C_YU_PLL_IN_FREQ (200 * 1000 * 1000) +/* Reference clock for Bluefield - 156 MHz. */ +#define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000) /* Constant used to determine the PLL frequency. */ #define MLNXBF_I2C_COREPLL_CONST 16384 @@ -1422,7 +1420,7 @@ static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) u32 corepll_val; u16 core_f; - pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ; + pad_frequency = MLXBF_I2C_PLL_IN_FREQ; corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); @@ -1457,7 +1455,7 @@ static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) u8 core_od, core_r; u32 core_f; - pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ; + pad_frequency = MLXBF_I2C_PLL_IN_FREQ; corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);