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Fri, 16 May 2025 05:44:16 -0700 From: Akhil R To: , , , , , , , , , , , , CC: Akhil R Subject: [PATCH v2 2/3] i2c: tegra: make reset an optional property Date: Fri, 16 May 2025 18:13:48 +0530 Message-ID: <20250516124349.58318-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20250516124349.58318-1-akhilrajeev@nvidia.com> References: <20250516124349.58318-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06C:EE_|DS0PR12MB7993:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a2a079b-396b-4035-dc1d-08dd947769f8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|7416014|376014|921020; X-Microsoft-Antispam-Message-Info: nbmRF11kYSzTDsgI3r0jjIrzLxTXNYmmF7tgfuNdXYXOG25Fv1oMQ1hAEml8gxqksQ0jVlw2xBE60Sq5Z77hlEuYwxYWRczO9+mfKYjrBjAWbpEHQTt1PW1lt3YqmNSYwNDvDqMTzX5OzK4l8rQRMJCf5FJ7eQ29pwpymO3SEMkJwZ3x0TggjthCYUAgax4OeyS8H4F1GXNEl09hg/y1og6eSEHxyHRBlgN8coAjBTn2K0enO2aaWDAsR/3iagfnbSxsq5K7RdHnNZ8UHjEZmkzcRj0AodZRCVSbTJK5q+iR7hMfj9KL0bivy90b4CQLEhA8XY5WDueeiz41ZDGmbAG134Q1xsvAlS48sglwpG4WhJXoLylwzoW5p45C2KJdVgsu4hA9kJkuIJnLbvE6OBCvXHrHRxUPWFaAF8QXQt+DAz9IHHoR/lRRNfqP+jx2Z7Kwx+xF8IN/gM1iFRTOpovYGoVKkboVVk2bzXQcd4ZglOkh0A4+jZH5ddIVEGem0dTNMGIrLISseebdjfGwB3L2M22q3KtVdCTQZ1QTyAyKVKsEwV+reCpx8AKeT+Pne+mk58lnXTT2gf0urftiX+4DRKS1B9A07JKWe/nHNMhLIZxshekvVD1R9UD2o59i3HWjauwZihw5/IwXvUQmV9Bn/5gLoiMpTcywmXl3xlSGVhBEgsB8i5Df5OFHfK8ZayBGIFOrdfvLQnU4oppG0sZqVG1P1driYrc3KrOhFpPGWHLSIY+/whEPrtrc35CIe2m11t7FyGkPQBIS7hSQecLfDpCBpWCeY8pQR40+g+N2HZ+yYVfVX8ydqTbMQ0Tr931oDMeWKru5CYNaNbgBmOHLpYZX8+u7jyDlC3xdRFJoIt1J50m/jBP9k8wH+romxiN0q1qPtWHG5vkFnkpD+e0G6FWnYsjDfvAaMViZTk90dkrlJ6vhZHJ5rYIljzm00dA8xLrSGidVxW7ElkZ6N0dPxuRkigLp2Fyarkc+OCHfm9yFefthZEpDkNl7hW5d0mI7vx0l2mLnSezea8KQYE5SErgtDCIZiAyQIER2Pjw175teyVw8OTYTOU8apXGMfMHbtFQ2ezwyrl0+fJWrsYT2HO/bpTi6u8Uax46ZDfMAVXfApy671ww0+jHjB8u+Rv0h8ZkvJr/OW5Hk4JgsyIIrA81adUKg/hfX10+liXOnFx0up3vqrE9mPpy5lYi5x/+aIicdxlZDZOIHCu0U+aLqqULMUssDeAAi/IT8ao0LisvZ5j/Rf2neU/O0V5H0IoXs3cFpZCvYJzgsM6NdkQcLDT98d+EvjtuqfFnes0/j5iPNqHmYUx0xVmj4nms9asE+nRbdNwqj0jI5GS8DzZyikq1upLxm6Ok1BpOLgbLO/nirlF3ln043Z3ilaaS1Vz1ljbiw8yaSG6anT2uCZqAW0C+ZyR2Jc/0lUKZ2UCNP9fqVoaMN/qS6+bkMKZM0/U15/C/Lkq5ljooMatiCXwwrerfowa7s1N2pagmbxOlt1tHkR932GFy2Ul4UHyFh4+MgJL5f84U24Txhxo8lxA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2025 12:44:35.3999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a2a079b-396b-4035-dc1d-08dd947769f8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06C.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7993 For controllers that has an internal software reset, make the reset property optional. This is useful in systems that choose to restrict reset control from Linux. Signed-off-by: Akhil R --- v1->v2: * Call devm_reset_control_get_optional_exclusive() unconditionally. * Add more delay based on HW recommendation. drivers/i2c/busses/i2c-tegra.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 87976e99e6d0..22ddbae9d847 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -134,6 +134,8 @@ #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) +#define I2C_MASTER_RESET_CNTRL 0x0a8 + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 @@ -184,6 +186,9 @@ enum msg_end_type { * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that * provides additional features and allows for longer messages to * be transferred in one go. + * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which + * provides an alternative to controller reset when configured as + * I2C master * @quirks: I2C adapter quirks for limiting write/read transfer size and not * allowing 0 length transfers. * @supports_bus_clear: Bus Clear support to recover from bus hang during @@ -213,6 +218,7 @@ struct tegra_i2c_hw_feature { bool has_multi_master_mode; bool has_slcg_override_reg; bool has_mst_fifo; + bool has_mst_reset; const struct i2c_adapter_quirks *quirks; bool supports_bus_clear; bool has_apb_dma; @@ -604,6 +610,20 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) return 0; } +static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev) +{ + if (!i2c_dev->hw->has_mst_reset) + return -EOPNOTSUPP; + + i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL); + udelay(2); + + i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL); + udelay(2); + + return 0; +} + static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; @@ -621,8 +641,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) */ if (handle) err = acpi_evaluate_object(handle, "_RST", NULL, NULL); - else + else if (i2c_dev->rst) err = reset_control_reset(i2c_dev->rst); + else + err = tegra_i2c_master_reset(i2c_dev); WARN_ON_ONCE(err); @@ -1467,6 +1489,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_apb_dma = true, @@ -1491,6 +1514,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_apb_dma = true, @@ -1515,6 +1539,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1539,6 +1564,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1563,6 +1589,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1587,6 +1614,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = false, @@ -1611,6 +1639,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_multi_master_mode = true, .has_slcg_override_reg = true, .has_mst_fifo = true, + .has_mst_reset = true, .quirks = &tegra194_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = false, @@ -1666,7 +1695,7 @@ static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) if (ACPI_HANDLE(i2c_dev->dev)) return 0; - i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); + i2c_dev->rst = devm_reset_control_get_optional_exclusive(i2c_dev->dev, "i2c"); if (IS_ERR(i2c_dev->rst)) return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), "failed to get reset control\n");