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Wed, 13 Nov 2024 16:14:32 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 42t0tmhvfq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 16:14:32 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4ADGEWRb032562; Wed, 13 Nov 2024 16:14:32 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.213.110.207]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4ADGEWE1032561 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 16:14:32 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934) id 9C48424055; Wed, 13 Nov 2024 21:44:31 +0530 (+0530) From: Mukesh Kumar Savaliya To: konrad.dybcio@linaro.org, andersson@kernel.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, conor+dt@kernel.org, agross@kernel.org, devicetree@vger.kernel.org, vkoul@kernel.org, linux@treblig.org, dan.carpenter@linaro.org, Frank.Li@nxp.com, konradybcio@kernel.org, bryan.odonoghue@linaro.org, krzk+dt@kernel.org, robh@kernel.org Cc: quic_vdadhani@quicinc.com, Mukesh Kumar Savaliya Subject: [PATCH v4 2/4] dmaengine: gpi: Add Lock and Unlock TRE support to access I2C exclusively Date: Wed, 13 Nov 2024 21:44:11 +0530 Message-Id: <20241113161413.3821858-3-quic_msavaliy@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241113161413.3821858-1-quic_msavaliy@quicinc.com> References: <20241113161413.3821858-1-quic_msavaliy@quicinc.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fz-8nwR4kyFmLNVb_Nc4Z61aSTQHRoLz X-Proofpoint-ORIG-GUID: fz-8nwR4kyFmLNVb_Nc4Z61aSTQHRoLz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130135 GSI DMA provides specific TREs(Transfer ring element) namely Lock and Unlock TRE. It provides mutually exclusive access to I2C controller from any of the processor(Apps,ADSP). Lock prevents other subsystems from concurrently performing DMA transfers and avoids disturbance to data path. Basically for shared I2C usecase, lock the SE(Serial Engine) for one of the processor, complete the transfer, unlock the SE. Apply Lock TRE for the first transfer of shared SE and Apply Unlock TRE for the last transfer. Also change MAX_TRE macro to 5 from 3 because of the two additional TREs. Signed-off-by: Mukesh Kumar Savaliya --- drivers/dma/qcom/gpi.c | 37 +++++++++++++++++++++++++++++++- include/linux/dma/qcom-gpi-dma.h | 6 ++++++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index 52a7c8f2498f..c9e71c576680 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020, Linaro Limited + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -65,6 +66,14 @@ /* DMA TRE */ #define TRE_DMA_LEN GENMASK(23, 0) +/* Lock TRE */ +#define TRE_LOCK BIT(0) +#define TRE_MINOR_TYPE GENMASK(19, 16) +#define TRE_MAJOR_TYPE GENMASK(23, 20) + +/* Unlock TRE */ +#define TRE_I2C_UNLOCK BIT(8) + /* Register offsets from gpi-top */ #define GPII_n_CH_k_CNTXT_0_OFFS(n, k) (0x20000 + (0x4000 * (n)) + (0x80 * (k))) #define GPII_n_CH_k_CNTXT_0_EL_SIZE GENMASK(31, 24) @@ -516,7 +525,7 @@ struct gpii { bool ieob_set; }; -#define MAX_TRE 3 +#define MAX_TRE 5 struct gpi_desc { struct virt_dma_desc vd; @@ -1637,6 +1646,19 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, struct gpi_tre *tre; unsigned int i; + /* create lock tre for first tranfser */ + if (i2c->shared_se && i2c->first_msg) { + tre = &desc->tre[tre_idx]; + tre_idx++; + + tre->dword[0] = 0; + tre->dword[1] = 0; + tre->dword[2] = 0; + tre->dword[3] = u32_encode_bits(1, TRE_LOCK); + tre->dword[3] |= u32_encode_bits(0, TRE_MINOR_TYPE); + tre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE); + } + /* first create config tre if applicable */ if (i2c->set_config) { tre = &desc->tre[tre_idx]; @@ -1695,6 +1717,19 @@ static int gpi_create_i2c_tre(struct gchan *chan, struct gpi_desc *desc, tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT); } + /* Unlock tre for last transfer */ + if (i2c->shared_se && i2c->last_msg && i2c->op != I2C_READ) { + tre = &desc->tre[tre_idx]; + tre_idx++; + + tre->dword[0] = 0; + tre->dword[1] = 0; + tre->dword[2] = 0; + tre->dword[3] = u32_encode_bits(1, TRE_I2C_UNLOCK); + tre->dword[3] |= u32_encode_bits(1, TRE_MINOR_TYPE); + tre->dword[3] |= u32_encode_bits(3, TRE_MAJOR_TYPE); + } + for (i = 0; i < tre_idx; i++) dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0], desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]); diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-dma.h index 6680dd1a43c6..8589c711afae 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -65,6 +65,9 @@ enum i2c_op { * @rx_len: receive length for buffer * @op: i2c cmd * @muli-msg: is part of multi i2c r-w msgs + * @shared_se: bus is shared between subsystems + * @bool first_msg: use it for tracking multimessage xfer + * @bool last_msg: use it for tracking multimessage xfer */ struct gpi_i2c_config { u8 set_config; @@ -78,6 +81,9 @@ struct gpi_i2c_config { u32 rx_len; enum i2c_op op; bool multi_msg; + bool shared_se; + bool first_msg; + bool last_msg; }; #endif /* QCOM_GPI_DMA_H */