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It affects the high and low pulse width of SCL line in high speed mode. The only legal values for this property are 100 and 400, which are used to calculate the tHIGH and tLOW periods for high speed mode. This property corresponds to IC_CAP_LOADING. clk-freq-optimized indicates that the hardware input clock frequency is reduced by reducing the internal latency. The property affects the high period and low period of the SCL line. The property conrresponds to IC_CLK_FREQ_OPTIMIZATION. Signed-off-by: Michael Wu --- .../bindings/i2c/snps,designware-i2c.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index 60035a787e5c..fc19e6a8b306 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -87,6 +87,20 @@ properties: This value is used to compute the tHIGH period. default: 300 + bus-capacitance-pf: + description: | + This property represents the bus capacitance in picofarad (pF). It + affects the high and low pulse width of SCL line in high speed mode. + The only legal values for this property are 100 and 400, which are used + to calculate the tHIGH and tLOW periods for high speed mode. + default: 100 + + clk-freq-optimized: + description: | + If the hardware input clock frequency is reduced by reducing the + internal latency, this property must be declared in the device tree. It + affects the high period and low period of SCL line. + dmas: items: - description: TX DMA Channel