@@ -12,15 +12,15 @@
#include <linux/platform_device.h>
#define UNIPHIER_FI2C_CR 0x00 /* control register */
-#define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
+#define UNIPHIER_FI2C_CR_MST BIT(3) /* controller mode */
#define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
#define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
#define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
#define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
-#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
+#define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (target addr) */
#define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
#define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
-#define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
+#define UNIPHIER_FI2C_SLAD 0x0c /* target address */
#define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
#define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
#define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
@@ -96,7 +96,7 @@ static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
/*
- * TX-FIFO stores slave address in it for the first access.
+ * TX-FIFO stores target address in it for the first access.
* Decrement the counter.
*/
if (first)
@@ -252,7 +252,7 @@ static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr,
/* do not use TX byte counter */
writel(0, priv->membase + UNIPHIER_FI2C_TBC);
- /* set slave address */
+ /* set target address */
writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
priv->membase + UNIPHIER_FI2C_DTTX);
/*
@@ -288,7 +288,7 @@ static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
uniphier_fi2c_set_irqs(priv);
- /* set slave address with RD bit */
+ /* set target address with RD bit */
writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
priv->membase + UNIPHIER_FI2C_DTTX);
}
@@ -310,9 +310,8 @@ static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
i2c_recover_bus(&priv->adap);
}
-static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
- struct i2c_msg *msg, bool repeat,
- bool stop)
+static int uniphier_fi2c_xfer_one(struct i2c_adapter *adap, struct i2c_msg *msg,
+ bool repeat, bool stop)
{
struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
bool is_read = msg->flags & I2C_M_RD;
@@ -340,7 +339,7 @@ static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
uniphier_fi2c_tx_init(priv, msg->addr, repeat);
/*
- * For a repeated START condition, writing a slave address to the FIFO
+ * For a repeated START condition, writing a target address to the FIFO
* kicks the controller. So, the UNIPHIER_FI2C_CR register should be
* written only for a non-repeated START condition.
*/
@@ -403,8 +402,7 @@ static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
return 0;
}
-static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
- struct i2c_msg *msgs, int num)
+static int uniphier_fi2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
struct i2c_msg *msg, *emsg = msgs + num;
bool repeat = false;
@@ -418,7 +416,7 @@ static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
/* Emit STOP if it is the last message or I2C_M_STOP is set. */
bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
- ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop);
+ ret = uniphier_fi2c_xfer_one(adap, msg, repeat, stop);
if (ret)
return ret;
@@ -434,7 +432,7 @@ static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
}
static const struct i2c_algorithm uniphier_fi2c_algo = {
- .master_xfer = uniphier_fi2c_master_xfer,
+ .xfer = uniphier_fi2c_xfer,
.functionality = uniphier_fi2c_functionality,
};
Change the wording of this driver wrt. the newest I2C v7 and SMBus 3.2 specifications and replace "master/slave" with more appropriate terms. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- drivers/i2c/busses/i2c-uniphier-f.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-)