From patchwork Thu Apr 25 08:21:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Bonnefille X-Patchwork-Id: 792151 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52A4F78C68; Thu, 25 Apr 2024 08:23:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714033388; cv=none; b=u91YG/w78CDFygSOruFVrkfi79XeFdleJmeMqU8aL+K7X9tRHDOif0/1E3EtvUQ81A/i0s0w6Ql7cYrTAlT5X/LqFzE2zwNb3ZYJw1ES3WA+DbFh1afUhiAlwkUYVuCB6nxZzqjtoJ3xTVZF2e5ZWKglf3pyxMp0RmeygUb7IQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714033388; c=relaxed/simple; bh=NSM6seXuH/Sllgc0h8ZbgbNftjPauWswl+UZ39HsJv0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z39KgExGNYT4fg6G5BUdIIwzzzU9gbnS3PvqMto7rsIuHbmytt7aPHnXujVUWiJ91prje66btydWewpnWW7N70gE/kvP78W6Agv1I08WE/dkzWrVrONHuo8r4idYltlo7WwBIyFSvSiF9140gSMrGZvx2rEInnfUiEEc32vW6xw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=fA57+TxG; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="fA57+TxG" Received: by mail.gandi.net (Postfix) with ESMTPSA id CFF8920009; Thu, 25 Apr 2024 08:23:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1714033384; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wNBhZc5P3FFJ7PgVYztZ5Wmu9O6JEWzPXLoqXVlXc70=; b=fA57+TxGB/4H7ZGTgztIdQHhKXNEN8N2TG15Rwx1WZZFO5f2JAtLjW8NFRHpwsKcf28Yi/ wy4Dy1dSJaE0djsTyxDOgWlspACp5pqXHYwr0/mcEkXmHbW4DGG+QtVHGJmKRWvk2hNuQe zFpMG4lGuwHhQOlJfGX8Wyi4VVhBBmAvZ5T8ysshf3SO/z1YxGXb5xb+IWvMuLWWOwdcln fjffGGDGD+6ykKsnDiZYuAbOoY2AkLMqbW8ZuRnaiRb6XD48Rq+iUXmrvwYIlzvXyJb4ei 1chjeUhcLK9FtCNU2UkMUldRdiK0WeQu0ZvtmH5yzyhh4pasN2n4JJWx3qFvlw== From: Thomas Bonnefille To: jszhang@kernel.org, guoren@kernel.org, wefu@redhat.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: miquel.raynal@bootlin.com, thomas.petazzoni@bootlin.com, linux-riscv@lists.infradead.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, Thomas Bonnefille Subject: [PATCH 3/4] riscv: dts: thead: Add TH1520 I2C nodes Date: Thu, 25 Apr 2024 10:21:34 +0200 Message-ID: <20240425082138.374445-4-thomas.bonnefille@bootlin.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240425082138.374445-1-thomas.bonnefille@bootlin.com> References: <20240425082138.374445-1-thomas.bonnefille@bootlin.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: thomas.bonnefille@bootlin.com Add nodes for the five I2C on the T-Head TH1520 RISCV SoC. All the I2C nodes are fed with the same clock named i2c_ic_clk. As there is currently no clock support, the i2c_ic_clk is exposed through a fixed-clock to mimic the existing nodes. Signed-off-by: Thomas Bonnefille --- arch/riscv/boot/dts/thead/th1520.dtsi | 66 +++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index d2fa25839012..86ae507576dc 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -153,6 +153,12 @@ sdhci_clk: sdhci-clock { #clock-cells = <0>; }; + i2c_ic_clk: i2c-clock { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -258,6 +264,36 @@ portc: gpio-controller@0 { }; }; + i2c0: i2c@ffe7f20000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f20000 0x0 0x4000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&i2c_ic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ffe7f24000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f24000 0x0 0x4000>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&i2c_ic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffe7f28000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f28000 0x0 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&i2c_ic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio3: gpio@ffe7f38000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f38000 0x0 0x1000>; @@ -312,6 +348,16 @@ portb: gpio-controller@0 { }; }; + i2c2: i2c@ffec00c000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xec00c000 0x0 0x4000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&i2c_ic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; @@ -322,6 +368,16 @@ uart2: serial@ffec010000 { status = "disabled"; }; + i2c3: i2c@ffec014000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xec014000 0x0 0x4000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&i2c_ic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; @@ -394,6 +450,16 @@ uart5: serial@fff7f0c000 { status = "disabled"; }; + i2c5: i2c@fff7f2c000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xf7f2c000 0x0 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&i2c_ic_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>;