From patchwork Fri Jul 28 12:00:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piyush Malgujar X-Patchwork-Id: 708152 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22FD8C001DE for ; Fri, 28 Jul 2023 12:01:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236384AbjG1MBL (ORCPT ); Fri, 28 Jul 2023 08:01:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236407AbjG1MAy (ORCPT ); Fri, 28 Jul 2023 08:00:54 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87C6F44BC; Fri, 28 Jul 2023 05:00:41 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36SA5iXY031978; Fri, 28 Jul 2023 05:00:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=RlQP+kX8ddsyp38Rtg1jEa0aQtyutbdd7ExMfBYXBu8=; b=SI3PUFyMXtcMBUQX8UlIylx+rEzJDosUdeetXZqn7fkmdRcWNMpaGoZx/nWfx4DfRwOY 69tnXkYwQ6/VdL7qy8ls9SaJDJ5V1/Y6zkU7min77bW4W7nY23wQpkNstXS/ytZnomLs IjScUMWkx1sV3NJuXdkoX93pBOlMyBTDI/Wrm/w646QIV+1nuWEjAZnJFbiy2sRwRjkG W6tgdHZDGk3pzbzyFTNuU9NrMSgdnDk5oGa7l2OWS81V3sGmKU0G0fh52Uy1zKuFkTfR 1MFpgrd7eiwWzeP4qh4N2iw39NgqlzTNXyahSlUjqFfZ6CmHu0b5jeu+NzpPm+dvCycz yw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3s389rxam6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 28 Jul 2023 05:00:37 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 28 Jul 2023 05:00:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 28 Jul 2023 05:00:35 -0700 Received: from localhost.localdomain (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id B38F93F705A; Fri, 28 Jul 2023 05:00:35 -0700 (PDT) From: Piyush Malgujar To: , , , CC: , , , Piyush Malgujar Subject: [PATCH v2 1/4] i2c: thunderx: Clock divisor logic changes Date: Fri, 28 Jul 2023 05:00:01 -0700 Message-ID: <20230728120004.19680-2-pmalgujar@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230728120004.19680-1-pmalgujar@marvell.com> References: <20230728120004.19680-1-pmalgujar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: aHPp95bITbLq_v3SezGcLLSCvDWJEqdt X-Proofpoint-GUID: aHPp95bITbLq_v3SezGcLLSCvDWJEqdt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Suneel Garapati Handle changes to clock divisor logic for OcteonTX2 SoC family using subsystem ID and using default reference clock source as 100MHz. Signed-off-by: Suneel Garapati Signed-off-by: Piyush Malgujar Acked-by: Andi Shyti --- drivers/i2c/busses/i2c-octeon-core.c | 29 ++++++++++++++++++++---- drivers/i2c/busses/i2c-octeon-core.h | 17 ++++++++++++++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 6 +++++ 3 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c index 845eda70b8cab52a0453c9f4cb545010fba4305d..1d8e1f4ad859dc44c08629637530842a0ed50bc4 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "i2c-octeon-core.h" @@ -658,31 +659,51 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) void octeon_i2c_set_clock(struct octeon_i2c *i2c) { int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; - int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; + int mdiv_min = 2; + /* starting value on search for lowest diff */ + const int huge_delta = INITIAL_DELTA_HZ; + /* + * Find divisors to produce target frequency, start with large delta + * to cover wider range of divisors, note thp = TCLK half period. + */ + unsigned int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = huge_delta; + + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) { + thp = 0x3; + mdiv_min = 0; + } for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) { /* * An mdiv value of less than 2 seems to not work well * with ds1337 RTCs, so we constrain it to larger values. */ - for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) { + for (mdiv_idx = 15; mdiv_idx >= mdiv_min && delta_hz != 0; mdiv_idx--) { /* * For given ndiv and mdiv values check the * two closest thp values. */ tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10; tclk *= (1 << ndiv_idx); - thp_base = (i2c->sys_freq / (tclk * 2)) - 1; + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) + thp_base = (i2c->sys_freq / tclk) - 2; + else + thp_base = (i2c->sys_freq / (tclk * 2)) - 1; for (inc = 0; inc <= 1; inc++) { thp_idx = thp_base + inc; if (thp_idx < 5 || thp_idx > 0xff) continue; - foscl = i2c->sys_freq / (2 * (thp_idx + 1)); + if (octeon_i2c_is_otx2(to_pci_dev(i2c->dev))) + foscl = i2c->sys_freq / (thp_idx + 2); + else + foscl = i2c->sys_freq / + (2 * (thp_idx + 1)); foscl = foscl / (1 << ndiv_idx); foscl = foscl / (mdiv_idx + 1) / 10; diff = abs(foscl - i2c->twsi_freq); + /* Use it if smaller diff from target */ if (diff < delta_hz) { delta_hz = diff; thp = thp_idx; diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h index 9bb9f64fdda0392364638ecbaafe3fab5612baf6..694c24cecb7b144c1021549d1661b040c21bb998 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -7,6 +7,7 @@ #include #include #include +#include /* Controller command patterns */ #define SW_TWSI_V BIT_ULL(63) /* Valid bit */ @@ -98,6 +99,8 @@ struct octeon_i2c_reg_offset { #define TWSI_INT(x) (x->roff.twsi_int) #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) +#define INITIAL_DELTA_HZ 1000000 + struct octeon_i2c { wait_queue_head_t queue; struct i2c_adapter adap; @@ -211,6 +214,20 @@ static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c)); } +#define PCI_SUBSYS_DEVID_9XXX 0xB +/** + * octeon_i2c_is_otx2 - check for chip ID + * @pdev: PCI dev structure + * + * Returns TRUE if OcteonTX2, FALSE otherwise. + */ +static inline bool octeon_i2c_is_otx2(struct pci_dev *pdev) +{ + u32 chip_id = (pdev->subsystem_device >> 12) & 0xF; + + return (chip_id == PCI_SUBSYS_DEVID_9XXX); +} + /* Prototypes */ irqreturn_t octeon_i2c_isr(int irq, void *dev_id); int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thunderx-pcidrv.c index a77cd86fe75ed7401bc041b27c651b9fedf67285..eecd27f9f1730e522dcccafc9f12ea891a3b59ef 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -205,6 +205,12 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, if (ret) goto error; + /* + * For OcteonTX2 chips, set reference frequency to 100MHz + * as refclk_src in TWSI_MODE register defaults to 100MHz. + */ + if (octeon_i2c_is_otx2(pdev)) + i2c->sys_freq = 100000000; octeon_i2c_set_clock(i2c); i2c->adap = thunderx_i2c_ops;