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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id p5-20020adfce05000000b002d64fcb362dsm19192398wrn.111.2023.03.27.01.28.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 01:28:07 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 27 Mar 2023 10:27:57 +0200 Subject: [PATCH v5 1/2] arm64: dts: mediatek: add i2c support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20221122-mt8365-i2c-support-v5-1-6e4f3b54937f@baylibre.com> References: <20221122-mt8365-i2c-support-v5-0-6e4f3b54937f@baylibre.com> In-Reply-To: <20221122-mt8365-i2c-support-v5-0-6e4f3b54937f@baylibre.com> To: Qii Wang , Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , Rob Herring , AngeloGioacchino Del Regno , Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2696; i=amergnat@baylibre.com; h=from:subject:message-id; bh=751COW4mlyt6NiZw3ZmEVilTCKVZTkOYnz6i1pHU/mc=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkIVOVvwFm7qKdwZ5fqAIYMGktI6dKizeGbo8hx4Vw M+z3ib6JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZCFTlQAKCRArRkmdfjHURS6mD/ 91U/H9o3Iw//cFCuK0mX1vV/fLdKa97DGN2ufyavXj+EIOEP2fyuPl99rsk+I75f22AWZL7Huchr7/ 7Un6yH9x0pgxIeA6btYsxNmcfSTNxKV0Zpm2yyBAZu5S2Il9b24eC7QuUWpQnoZekAhQDJnAomDyqI c+yAwJgszvZyeSnARrUzyjFAM1E9hiB46/VxBomQmS4qUF+8Jokk+xY6RvEr46TZysSA3jhvWn7uJY IJNa7E6IQUST8XWeTmZH86DwJukLcZcSz5hDLPvjO4IseLFF5zYaL1O12kdRaMxX3juJSBvBh6vlDF Yl9DrF3uNa9bHaGO5pigeTm7xKXSLAeAYv/FS5k+ILRQGOselZlEocceg9Fu+O11ssCHe6ArS7EZdD qHxmmG3DBIk43L2RCfqYom4rDrBx6QANBbzc1WfXqwGi4ncBs/6AdxzZE5s8Ok9EyHvBR9Ea2/g3WI 4U0/ifwyO/bEGQHoIAVkdNvDGptUOHAVcXznUtB8V93G5ju3Lu38EjBU7BgCd7UKfOfooX355KkkDi siiDNUnNQdAWTsX3oxqmYp5tHirvCCQsEenvPO9xQirAiZRd+g85tPqx+A/m2L+HkW/RNeYbCZV0Rk CjLndADLN2vSn53AaED+wNEfeCqswSy4rdhKDK5hG9UYEg/fvc9B60hdtc1w== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org There are four I2C master channels in MT8365 with a same HW architecture. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 15ac4c1f0966..b70f4d256f63 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -282,6 +282,42 @@ pwm: pwm@11006000 { clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi: spi@1100a000 { compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; reg = <0 0x1100a000 0 0x100>; @@ -295,6 +331,18 @@ spi: spi@1100a000 { status = "disabled"; }; + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ssusb: usb@11201000 { compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;