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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id bu9-20020a056000078900b002be1dcb6efbsm8738701wrb.9.2023.01.19.09.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 09:09:13 -0800 (PST) From: Alexandre Mergnat Date: Thu, 19 Jan 2023 18:08:53 +0100 Subject: [PATCH v2 2/3] arm64: dts: mediatek: add i2c support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20221122-mt8365-i2c-support-v2-2-e4c7c514e781@baylibre.com> References: <20221122-mt8365-i2c-support-v2-0-e4c7c514e781@baylibre.com> In-Reply-To: <20221122-mt8365-i2c-support-v2-0-e4c7c514e781@baylibre.com> To: Qii Wang , Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandre Mergnat , Fabien Parent , Rob Herring , linux-i2c@vger.kernel.org, AngeloGioacchino Del Regno , devicetree@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2420; i=amergnat@baylibre.com; h=from:subject:message-id; bh=3qzpqDF5qfsZV4KFvmmkuAuRkJdkE+nj1hKT6VsiEUg=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjyXk2DWa0vY1hFgtNfd4QTVahKvP0ZkrY5dVux337 SpiXGkOJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY8l5NgAKCRArRkmdfjHURdyLD/ 0STpm6+z3UnD9cuzRfXOhPP7k4MXyxU7tyhUjhe7GaHnlEHZbXPMJ+L0M05jPyPCla0vFPcMDJJyrM 9Zg1Mkl3SnkvD2sWiVJg6uvZsqIGnPpBeo33iKV3EmpjMxw6Shw1NPNb61FpEQX0fdriFOnoBvTgC1 vybtbcFuEFu2QgKKRlhMo2TKUqBb5WlaPBqZD0LpAv0IQM+BR05th9TDcjpREv8WXkgu5s75T/sn8a /hq780PeuNb4AC9ququQ7mixh73ajBrCSuCoWBORqsYOkvegWqklX5G/tAd7r43F+6t2inGtnEVVgD 5Jd3BB9r+Mma7U2VmM7bBCFPMDnem6Q1vg/KBogizDT5EQelJTEsF1QmMxj+yoLjVhTSvNaofvYba1 GmKKacDExAHvwAMiOkebr26DzK30nEkmsxitcA5mo1QF9RRgAHyuQV0buR2IxZSM/7G2Se3LljeLXu EJiYLwjTGrxSWWqkYa024eK0IO0KS//GwNgrm3ckgyiCFnx4848OuqzUF6F8jYBYgmZ5F2o0RBIU7q VZ3oTKfPMUgfLatolft/J5pvr9bnz4bK0dr2V4QcQGLjy+5J2VvpPEQj+0haNMoM20gG0G2vebEWE8 uJ7f2udZP3tXCg8UuXwxInHrgexGGnbYvXgJyMo2g3KHprRrOP5iVKt8TieA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org There are four I2C master channels in MT8365 with a same HW architecture. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 52 ++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index a32f2b7507be..013beb50b4aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -282,6 +282,58 @@ pwm: pwm@11006000 { clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi: spi@1100a000 { compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; reg = <0 0x1100a000 0 0x100>;