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H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(376002)(346002)(136003)(396003)(46966006)(36840700001)(40470700004)(426003)(336012)(47076005)(356005)(7696005)(921005)(26005)(2616005)(1076003)(186003)(81166007)(36860700001)(83380400001)(82740400003)(8936002)(5660300002)(7416002)(70586007)(70206006)(8676002)(4326008)(40480700001)(82310400005)(2906002)(107886003)(6666004)(478600001)(41300700001)(40460700003)(316002)(110136005)(36756003)(86362001)(2101003)(83996005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2022 12:23:57.1569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d233c41-09fe-41f4-717e-08da81ddb05a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT097.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4202 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dma properties to support GPCDMA in Tegra234 I2C Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 32 ++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 81a0f599685f..34026ca80b36 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -737,6 +737,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C1>; reset-names = "i2c"; + dmas = <&gpcdma 21>, <&gpcdma 21>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; cam_i2c: i2c@3180000 { @@ -752,6 +756,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C3>; reset-names = "i2c"; + dmas = <&gpcdma 23>, <&gpcdma 23>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; dp_aux_ch1_i2c: i2c@3190000 { @@ -767,6 +775,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C4>; reset-names = "i2c"; + dmas = <&gpcdma 26>, <&gpcdma 26>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; dp_aux_ch0_i2c: i2c@31b0000 { @@ -782,6 +794,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C6>; reset-names = "i2c"; + dmas = <&gpcdma 30>, <&gpcdma 30>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; dp_aux_ch2_i2c: i2c@31c0000 { @@ -797,6 +813,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C7>; reset-names = "i2c"; + dmas = <&gpcdma 27>, <&gpcdma 27>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; dp_aux_ch3_i2c: i2c@31e0000 { @@ -812,6 +832,10 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C9>; reset-names = "i2c"; + dmas = <&gpcdma 31>, <&gpcdma 31>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; spi@3270000 { @@ -1109,6 +1133,10 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C2>; reset-names = "i2c"; + dmas = <&gpcdma 22>, <&gpcdma 22>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; gen8_i2c: i2c@c250000 { @@ -1125,6 +1153,10 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C8>; reset-names = "i2c"; + dmas = <&gpcdma 0>, <&gpcdma 0>; + dma-names = "rx", "tx"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; }; rtc@c2a0000 {