From patchwork Sat Aug 6 10:02:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kewei Xu X-Patchwork-Id: 596295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 543E5C3F6B0 for ; Sat, 6 Aug 2022 10:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241839AbiHFKDQ (ORCPT ); Sat, 6 Aug 2022 06:03:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241825AbiHFKDP (ORCPT ); Sat, 6 Aug 2022 06:03:15 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43E1C167E5; Sat, 6 Aug 2022 03:03:09 -0700 (PDT) X-UUID: 5d76dbe6f7f3423bb0b91f043b50878b-20220806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BM1cHQPutbJT/weJKIewcPcyGXF9P1GaLV7WSvTfPNE=; b=fqbbk+TpzkI7vUtJwxBxQWf4f8jR8TyX7ZGmQXpJ97u6v1aFdSCfum1xJ/h0Ou9MnlFsBW7GHfJwHMTukmTRISwCn0dyfqrUEbIiqXu7V6A41Q/k3LyfnWsucf/GG3R3PMbCDDb5d4ecDhC9pPc11+Yh9i17w9DT8dDxuwUkaQk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:223c9c0d-960e-4efb-a218-e16a215f1a5f, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:0f94e32, CLOUDID:a585ef9b-da39-4e3b-a854-56c7d2111b46, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 5d76dbe6f7f3423bb0b91f043b50878b-20220806 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1680764740; Sat, 06 Aug 2022 18:03:01 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Sat, 6 Aug 2022 18:02:59 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 6 Aug 2022 18:02:58 +0800 From: To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v5 2/2] i2c: mediatek: add i2c compatible for MT8188 Date: Sat, 6 Aug 2022 18:02:49 +0800 Message-ID: <20220806100249.12375-2-kewei.xu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220806100249.12375-1-kewei.xu@mediatek.com> References: <20220806100249.12375-1-kewei.xu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Kewei Xu Add i2c compatible for MT8188 and added mt_i2c_regs_v3[], since MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94. Signed-off-by: Kewei Xu Reviewed-by: AngeloGioacchino Del Regno --- v5: modify the order of mt_i2c_regs_v3[] members and add Reviewed-by owner. v4: no changes V3: no changes V2: added mt_i2c_regs_v3[] to replace slave_addr_version. --- drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 8e6985354fd5..bd8abba3d1c9 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = { [OFFSET_DCM_EN] = 0xf88, }; +static const u16 mt_i2c_regs_v3[] = { + [OFFSET_DATA_PORT] = 0x0, + [OFFSET_INTR_MASK] = 0x8, + [OFFSET_INTR_STAT] = 0xc, + [OFFSET_CONTROL] = 0x10, + [OFFSET_TRANSFER_LEN] = 0x14, + [OFFSET_TRANSAC_LEN] = 0x18, + [OFFSET_DELAY_LEN] = 0x1c, + [OFFSET_TIMING] = 0x20, + [OFFSET_START] = 0x24, + [OFFSET_EXT_CONF] = 0x28, + [OFFSET_LTIMING] = 0x2c, + [OFFSET_HS] = 0x30, + [OFFSET_IO_CONFIG] = 0x34, + [OFFSET_FIFO_ADDR_CLR] = 0x38, + [OFFSET_SDA_TIMING] = 0x3c, + [OFFSET_TRANSFER_LEN_AUX] = 0x44, + [OFFSET_CLOCK_DIV] = 0x48, + [OFFSET_SOFTRESET] = 0x50, + [OFFSET_MULTI_DMA] = 0x8c, + [OFFSET_SCL_MIS_COMP_POINT] = 0x90, + [OFFSET_SLAVE_ADDR] = 0x94, + [OFFSET_DEBUGSTAT] = 0xe4, + [OFFSET_DEBUGCTRL] = 0xe8, + [OFFSET_FIFO_STAT] = 0xf4, + [OFFSET_FIFO_THRESH] = 0xf8, + [OFFSET_DCM_EN] = 0xf88, +}; + struct mtk_i2c_compatible { const struct i2c_adapter_quirks *quirks; const u16 *regs; @@ -442,6 +471,19 @@ static const struct mtk_i2c_compatible mt8186_compat = { .max_dma_support = 36, }; +static const struct mtk_i2c_compatible mt8188_compat = { + .regs = mt_i2c_regs_v3, + .pmic_i2c = 0, + .dcm = 0, + .auto_restart = 1, + .aux_len_reg = 1, + .timing_adjust = 1, + .dma_sync = 0, + .ltiming_adjust = 1, + .apdma_sync = 1, + .max_dma_support = 36, +}; + static const struct mtk_i2c_compatible mt8192_compat = { .quirks = &mt8183_i2c_quirks, .regs = mt_i2c_regs_v2, @@ -465,6 +507,7 @@ static const struct of_device_id mtk_i2c_of_match[] = { { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat }, + { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat }, { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat }, {} };