From patchwork Mon Mar 8 12:20:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 396354 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F9B4C4332D for ; Mon, 8 Mar 2021 12:21:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D9B9F651C7 for ; Mon, 8 Mar 2021 12:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230457AbhCHMUw (ORCPT ); Mon, 8 Mar 2021 07:20:52 -0500 Received: from mga12.intel.com ([192.55.52.136]:52723 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230184AbhCHMUm (ORCPT ); Mon, 8 Mar 2021 07:20:42 -0500 IronPort-SDR: PZ5EcfDbbkwuNTBHD7gK4UCo2DL3cJK7ZWXRXrV/X7eUwgBdbjmS/ay3nGTG8OxLFIhp1zFzZG C5RrnkMceafA== X-IronPort-AV: E=McAfee;i="6000,8403,9916"; a="167288037" X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="167288037" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2021 04:20:41 -0800 IronPort-SDR: fSv4514lS+BwTAYRGvBpsn5EFCTYomMuaTpSj1R21DCWGD1sXJ7lzEfdUIRNcnJcPhrvSMUVRR AMt/kuKR0zNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,232,1610438400"; d="scan'208";a="588032254" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 08 Mar 2021 04:20:37 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 1E405490; Mon, 8 Mar 2021 14:20:38 +0200 (EET) From: Andy Shevchenko To: Wolfram Sang , Jean Delvare , Lee Jones , Andy Shevchenko , Tan Jui Nee , Jim Quinlan , Jonathan Yong , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jean Delvare , Peter Tyser , hdegoede@redhat.com, henning.schild@siemens.com Subject: [PATCH v1 4/7] mfd: lpc_ich: Factor out lpc_ich_enable_spi_write() Date: Mon, 8 Mar 2021 14:20:17 +0200 Message-Id: <20210308122020.57071-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> References: <20210308122020.57071-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Factor out duplicate code to lpc_ich_enable_spi_write() helper function. Signed-off-by: Andy Shevchenko --- drivers/mfd/lpc_ich.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 3bbb29a7e7a5..3a19ed57260e 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -1083,12 +1083,21 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) return ret; } +static void lpc_ich_test_spi_write(struct pci_dev *dev, unsigned int devfn, + struct intel_spi_boardinfo *info) +{ + u32 bcr; + + pci_bus_read_config_dword(dev->bus, devfn, BCR, &bcr); + info->writeable = !!(bcr & BCR_WPD); +} + static int lpc_ich_init_spi(struct pci_dev *dev) { struct lpc_ich_priv *priv = pci_get_drvdata(dev); struct resource *res = &intel_spi_res[0]; struct intel_spi_boardinfo *info; - u32 spi_base, rcba, bcr; + u32 spi_base, rcba; info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); if (!info) @@ -1112,8 +1121,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev) res->start = spi_base + SPIBASE_LPT; res->end = res->start + SPIBASE_LPT_SZ - 1; - pci_read_config_dword(dev, BCR, &bcr); - info->writeable = !!(bcr & BCR_WPD); + lpc_ich_test_spi_write(dev, dev->devfn, info); } break; @@ -1134,8 +1142,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev) res->start = spi_base & 0xfffffff0; res->end = res->start + SPIBASE_APL_SZ - 1; - pci_bus_read_config_dword(bus, spi, BCR, &bcr); - info->writeable = !!(bcr & BCR_WPD); + lpc_ich_test_spi_write(dev, spi, info); } pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);