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Thu, 22 Sep 2022 01:45:30 -0700 Envelope-to: michal.simek@amd.com, radhey.shyam.pandey@amd.com, shubhrajyoti.datta@amd.com, srinivas.goud@amd.com, linux-arm-kernel@lists.infradead.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.23.64.6] (port=54840 helo=xhdvnc106.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1obHpp-0005X3-TM; Thu, 22 Sep 2022 01:45:30 -0700 Received: by xhdvnc106.xilinx.com (Postfix, from userid 90444) id EA82D610BE; Thu, 22 Sep 2022 14:15:05 +0530 (IST) From: Manikanta Guntupalli To: , , , , CC: , , , Raviteja Narayanam , Manikanta Guntupalli Subject: [PATCH V2 2/9] i2c: xiic: Fix Rx and Tx paths in standard mode Date: Thu, 22 Sep 2022 14:14:47 +0530 Message-ID: <1663836294-5698-3-git-send-email-manikanta.guntupalli@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1663836294-5698-1-git-send-email-manikanta.guntupalli@xilinx.com> References: <1663836294-5698-1-git-send-email-manikanta.guntupalli@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1NAM02FT050:EE_|BL3PR02MB7906:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d69a598-3254-4a9b-461f-08da9c76dab5 X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(136003)(376002)(396003)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(6266002)(26005)(82740400003)(40460700003)(70586007)(316002)(42186006)(70206006)(2906002)(7636003)(40480700001)(356005)(110136005)(36860700001)(36756003)(2616005)(336012)(54906003)(82310400005)(6666004)(478600001)(83380400001)(107886003)(44832011)(186003)(8936002)(5660300002)(426003)(4326008)(41300700001)(8676002)(47076005)(102446001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 08:45:51.4171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d69a598-3254-4a9b-461f-08da9c76dab5 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT050.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR02MB7906 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Raviteja Narayanam When a combined message request comes from user space, the controller has to initiate repeated start sequence. In standard mode, this repeated start sequence is corrupted if there is still data in the Tx FIFO. So, always make sure that all the bytes are completely transmitted out of the FIFO by waiting for TXEMPTY, if the previous message is of Tx type. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli --- drivers/i2c/busses/i2c-xiic.c | 53 +++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 2aa43e067fee..79802fffa26c 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -61,6 +61,7 @@ enum xiic_endian { * @state: See STATE_ * @singlemaster: Indicates bus is single master * @dynamic: Mode of controller + * @prev_msg_tx: Previous message is Tx */ struct xiic_i2c { struct device *dev; @@ -78,6 +79,7 @@ struct xiic_i2c { enum xilinx_i2c_state state; bool singlemaster; bool dynamic; + bool prev_msg_tx; }; #define XIIC_MSB_OFFSET 0 @@ -280,6 +282,24 @@ static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) return 0; } +static int xiic_wait_tx_empty(struct xiic_i2c *i2c) +{ + u8 isr; + unsigned long timeout; + + timeout = jiffies + XIIC_I2C_TIMEOUT; + for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); + !(isr & XIIC_INTR_TX_EMPTY_MASK); + isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) { + if (time_after(jiffies, timeout)) { + dev_err(i2c->dev, "Timeout waiting at Tx empty\n"); + return -ETIMEDOUT; + } + } + + return 0; +} + static int xiic_reinit(struct xiic_i2c *i2c) { int ret; @@ -685,6 +705,20 @@ static void xiic_start_recv(struct xiic_i2c *i2c) local_irq_restore(flags); } else { + /* + * If previous message is Tx, make sure that Tx FIFO is empty + * before starting a new transfer as the repeated start in + * standard mode can corrupt the transaction if there are + * still bytes to be transmitted in FIFO + */ + if (i2c->prev_msg_tx) { + int status; + + status = xiic_wait_tx_empty(i2c); + if (status) + return; + } + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); /* Set Receive fifo depth */ @@ -739,6 +773,8 @@ static void xiic_start_recv(struct xiic_i2c *i2c) /* Enable interrupts */ xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); + + i2c->prev_msg_tx = false; } static void xiic_start_send(struct xiic_i2c *i2c) @@ -773,6 +809,19 @@ static void xiic_start_send(struct xiic_i2c *i2c) xiic_fill_tx_fifo(i2c); } else { + /* + * If previous message is Tx, make sure that Tx FIFO is empty + * before starting a new transfer as the repeated start in + * standard mode can corrupt the transaction if there are + * still bytes to be transmitted in FIFO + */ + if (i2c->prev_msg_tx) { + int status; + + status = xiic_wait_tx_empty(i2c); + if (status) + return; + } /* Check if RSTA should be set */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); if (cr & XIIC_CR_MSMS_MASK) { @@ -803,6 +852,7 @@ static void xiic_start_send(struct xiic_i2c *i2c) XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK); } + i2c->prev_msg_tx = true; } static void __xiic_start_xfer(struct xiic_i2c *i2c) @@ -866,6 +916,9 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) /* Decide standard mode or Dynamic mode */ i2c->dynamic = true; + /* Initialize prev message type */ + i2c->prev_msg_tx = false; + /* * If number of messages is 1 and read length is > 255 bytes, * enter standard mode