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Sat, 22 Jan 2022 03:24:37 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v2 3/4] dt-bindings: Add headers for Tegra234 PWM Date: Sat, 22 Jan 2022 16:53:26 +0530 Message-ID: <1642850607-20664-4-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 78f82fc8-45fa-46cd-522c-08d9dd99c88a X-MS-TrafficTypeDiagnostic: MN2PR12MB3246:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1186; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PtZLbekLkiiV7GewUAC3t+88Ig7KznTTk+kMBJ7ErOsREq+e0xfC/ZgZPQNkOGAx0m5wKWTCvW5OIa3ar6A1R5EMgxmt5HjlGFHf29t1/+HRjawZLIfO3A0v0YPSBGgOjYTZ+4GKLIfxSdIVJilWXsfq43sC8dizBKe1pXCOmY/V3Semi7LfPrrJH45qYCDjrEJB7NbcsquP5xrwp5Y7y/JSMytt8bniUqUFgQPhcHMLw+CZXlzoJfiQ4kyreOgCBcsiBssD7UovhSvz4DAwUHJNgWpTIv48j6mj96woPUBeepBz9/H26exSeaIY2pvwfsV3QY9GOoCYMv3l47NrbHuUlIksZDl6CsrPIq0dip/CupwTDlvSWHwe7Muf6XNCzbQSNZ0vEVVnOUht6Cpp6SVxhcppvRDvi2IIxfi45X3+YBfHld86p9L+mPfPd84ljb6vqbRI3udz+h6sX+eInZhMxquG9kQxF9Iw1wOFBU9gMFOISlU5OLbPLo12pIypUOgpb6TlugVg9YcxKZE6C++HfrfmK4BnLHm2rfjkXjcb+FrOg2wIQHCcjxB2NlbK2DaB7lu71lR2p5kBfpK+PfzblsFWx3fPtoMM7AHFA+yKYDJ2eMOPzWKhKnmzyFVbMm15LnsilaMHzNnDjO0wY67PF1m32qXyFl0mOa3c7qvwNrQDL3F3owYyYhaRDxC+f4yRDSAkwPQ19NGUi1MiBCFPBkdPT1ygV9qg1bpwMd0+ZKh9EDxlz1B37Jwo99JwUa9ZCxLIflvXEMHfi5tY4yaQF+T3JClhxMgggTRLv6uocc+tqHBIGEbehy5A3fQKbha2WQwN52gROziEqV6kC9+7bqizkvhbVDkU0ktQrJ0= X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700004)(46966006)(36840700001)(40460700003)(336012)(36860700001)(70206006)(4326008)(70586007)(8936002)(508600001)(107886003)(36756003)(8676002)(86362001)(186003)(81166007)(5660300002)(26005)(83380400001)(2906002)(2616005)(356005)(921005)(47076005)(82310400004)(6666004)(7696005)(110136005)(426003)(316002)(36900700001)(2101003)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2022 11:24:41.2628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78f82fc8-45fa-46cd-522c-08d9dd99c88a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3246 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dt-bindings header files for PWM of Tegra234 Signed-off-by: Akhil R --- include/dt-bindings/clock/tegra234-clock.h | 17 +++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ 2 files changed, 25 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 5d05c19..9d17309 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -50,4 +50,21 @@ /** @brief PLLP clk output */ #define TEGRA234_CLK_PLLP_OUT0 102U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA234_CLK_PWM1 105U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA234_CLK_PWM2 106U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA234_CLK_PWM3 107U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA234_CLK_PWM4 108U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA234_CLK_PWM5 109U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA234_CLK_PWM6 110U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA234_CLK_PWM7 111U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA234_CLK_PWM8 112U + #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index e07e898..288524f 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -20,6 +20,14 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_PWM1 68U +#define TEGRA234_RESET_PWM2 69U +#define TEGRA234_RESET_PWM3 70U +#define TEGRA234_RESET_PWM4 71U +#define TEGRA234_RESET_PWM5 72U +#define TEGRA234_RESET_PWM6 73U +#define TEGRA234_RESET_PWM7 74U +#define TEGRA234_RESET_PWM8 75U /** @} */