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Sat, 22 Jan 2022 03:24:19 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v2 1/4] dt-bindings: Add headers for Tegra234 I2C Date: Sat, 22 Jan 2022 16:53:24 +0530 Message-ID: <1642850607-20664-2-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> References: <1642850607-20664-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1f13cda8-c4d7-4149-3b62-08d9dd99be08 X-MS-TrafficTypeDiagnostic: BY5PR12MB4244:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1186; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qfL5c121iUji5f8obuBbdscSb987g8QAZ3RgAABNFXyippvMTSFlgYztOpO37oq4QX7PpOe8APokghUdEVAdu6iKLC1i1zqV/rqQPKq61UGnphYEYuUXcr0uTwAoDtH7RZChOa0p6Q8DJJ4oGF84LszHradvrNUcmeBPLaZTnj0PQc5X1CK4CGtniS7vlMIIlgWFOZesch0+9DotkaHrvMI3nvxp1kaISEPQsMIu3ufNZbRAbM4ir5CZxUPBG0Wz2mzczU3ysZZpTUtR5lcuCzrXqEfHpCH/3szP0EvorQsaIEOef7Y0HYL5QxI5Zpl/SCYal4KzeH0J7T7gUwxy6T0vYiDuv4UnV29Ipv3ir5BB1dNl0bFX43ZsQurH+Wrvw3Sr7u8CfTMY2drUok7+soPS3+3Evn+yvlGnczY65/Nd60TMs+x2rffEVv1my2vySOKfiW+x7kUNNjJDIll0gjLCg0OtP4MEY6D4rxJkgPKRsDb+yIEp0l95I4E9PpZVo+KEbMZGrnhded3f1X+VjxsNHVJzvcOUk2naqqyO6yW5TtI8IJMT2q8HIKgInZqbo5NBs3uKcJc/TZoklm3op1TYm3F6OWEard0m36CDEf53TFcuNUW0oD+Zyvnmq/ZnKHNR/n/DXnyTbDjiCvGlW688vg+SnfL8ct2iJdR6InI24x4lUgWB5lnzvkKXAHvCSQUfaKrYCciJTdA1rxUNVnCrYDHusdtOl0Pd3jjGAZWD/23NRhAkgaIJc4U5B2ONpAouGiqVJ61E/1w3a2BLQwpDuxHwomov+hQnb3YAAovCwJ1CTso2Qyb7IZSjsoEEzXAmqSHJqD4YznNfPJkpGCpaOEy+LbtmzxvhoHHCD58= X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(36840700001)(40470700004)(46966006)(107886003)(2906002)(5660300002)(86362001)(8936002)(40460700003)(921005)(508600001)(26005)(70586007)(186003)(316002)(70206006)(7696005)(426003)(36756003)(356005)(47076005)(83380400001)(8676002)(110136005)(4326008)(2616005)(81166007)(336012)(6666004)(82310400004)(36860700001)(36900700001)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2022 11:24:23.6487 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f13cda8-c4d7-4149-3b62-08d9dd99be08 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4244 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dt-bindings header files for I2C controllers for Tegra234 Signed-off-by: Akhil R --- include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ 2 files changed, 27 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8d7e66e..5d05c19 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -30,5 +30,24 @@ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ +#define TEGRA234_CLK_I2C1 48U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA234_CLK_I2C2 49U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA234_CLK_I2C3 50U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA234_CLK_I2C4 51U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA234_CLK_I2C6 52U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA234_CLK_I2C7 53U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA234_CLK_I2C8 54U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA234_CLK_I2C9 55U + +/** @brief PLLP clk output */ +#define TEGRA234_CLK_PLLP_OUT0 102U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 50e13bc..e07e898 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -12,6 +12,14 @@ */ #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U +#define TEGRA234_RESET_I2C1 24U +#define TEGRA234_RESET_I2C2 29U +#define TEGRA234_RESET_I2C3 30U +#define TEGRA234_RESET_I2C4 31U +#define TEGRA234_RESET_I2C6 32U +#define TEGRA234_RESET_I2C7 33U +#define TEGRA234_RESET_I2C8 34U +#define TEGRA234_RESET_I2C9 35U /** @} */