From patchwork Sat Sep 12 05:57:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UWlpIFdhbmcgKOeOi+eQqik=?= X-Patchwork-Id: 254734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D650C433E2 for ; Sat, 12 Sep 2020 05:59:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F84620855 for ; Sat, 12 Sep 2020 05:59:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tB7yoDOW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725833AbgILF7m (ORCPT ); Sat, 12 Sep 2020 01:59:42 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:56593 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725808AbgILF7k (ORCPT ); Sat, 12 Sep 2020 01:59:40 -0400 X-UUID: f25248f627934c929426b30cf3561136-20200912 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=i9ffQliwWH6EmfVZu18WwAkTORgoZOjNhfKuRo1pCM0=; b=tB7yoDOWxPj3fjDSStcDiZ7Aj+hoy0lXlsZZHpMEuMeL/4tE2j14anyrae/f5qK9ITMl+mAi6F6hRg9obxIp9327UjXHuL8yytQ3euK0mGv7DWafqY3dXnX/K+eLc087j9YqBQDweuvWrFsdDo/3SbMtMxleZS2CUnf6RnBx40c=; X-UUID: f25248f627934c929426b30cf3561136-20200912 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1817924852; Sat, 12 Sep 2020 13:59:28 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 12 Sep 2020 13:59:26 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 12 Sep 2020 13:59:25 +0800 From: To: CC: , , , , , , , Subject: [PATCH] i2c: mediatek: Fix generic definitions for bus frequencies Date: Sat, 12 Sep 2020 13:57:26 +0800 Message-ID: <1599890246-21191-1-git-send-email-qii.wang@mediatek.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-MTK: N Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Qii Wang The master code needs to being sent when the speed is more than I2C_MAX_FAST_MODE_PLUS_FREQ instead of I2C_MAX_HIGH_SPEED_MODE_FREQ. Fix it. Signed-off-by: Qii Wang --- drivers/i2c/busses/i2c-mt65xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 1.9.1 Reviewed-by: Yingjoe Chen diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index efc1404..0cbdfbe 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -681,8 +681,8 @@ static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src, unsigned int cnt_mul; int ret = -EINVAL; - if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) - target_speed = I2C_MAX_FAST_MODE_PLUS_FREQ; + if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ) + target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ; max_step_cnt = mtk_i2c_max_step_cnt(target_speed); base_step_cnt = max_step_cnt; @@ -759,7 +759,7 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk) for (clk_div = 1; clk_div <= max_clk_div; clk_div++) { clk_src = parent_clk / clk_div; - if (target_speed > I2C_MAX_FAST_MODE_FREQ) { + if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) { /* Set master code speed register */ ret = mtk_i2c_calculate_speed(i2c, clk_src, I2C_MAX_FAST_MODE_FREQ,