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[v4,0/2] Compute HS HCNT and LCNT based on HW parameters

Message ID 20241003111525.779410-1-michael.wu@kneron.us
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Series Compute HS HCNT and LCNT based on HW parameters | expand

Message

Michael Wu Oct. 3, 2024, 11:15 a.m. UTC
In commit 35eba185fd1a ("i2c: designware: Calculate SCL timing parameter
for High Speed Mode") the SCL high period count and low period count for
high speed mode are calculated based on fixed tHIGH = 160 and tLOW = 120.
However, the set of two fixed values is only applicable to the combination
of hardware parameters IC_CAP_LOADING is 400 and IC_CLK_FREQ_OPTIMIZATION
is true. Outside of this combination, the SCL frequency may not reach
3.4 MHz because the fixed tHIGH and tLOW are not small enough.

Since there are no any registers controlling these two hardware parameters,
their values can only be declared through the device tree.

v4:
- yaml: re-formatting two properties' description
- yaml: enumeriate bus-capacitance-pf
- yaml: extand an existing example
- driver: modify the commit description
- driver: rename "bus-capacitance-pf" to "bus-capacitance-pF"

v3:
- add vendor prefix on new property name
- read new properties in i2c_dw_fw_parse_and_configure() directly
- in i2c_dw_set_timings_master() check dev->bus_capacitance_pf and then decide
  t_high and t_low

v2:
- provide more hardware information in dt-bindings
- rename "bus-loading" to "bus-capacitance-pf"
- call new i2c_dw_fw_parse_hw_params() in i2c_dw_fw_parse_and_configure() to
  parse hardware parameters from the device tree.

Michael Wu (2):
  dt-bindings: i2c: snps,designware-i2c: declare bus capacitance and clk
    freq optimized
  i2c: dwsignware: determine HS tHIGH and tLOW based on HW parameters

 .../bindings/i2c/snps,designware-i2c.yaml     | 18 +++++++++++++++
 drivers/i2c/busses/i2c-designware-common.c    |  5 ++++
 drivers/i2c/busses/i2c-designware-core.h      |  6 +++++
 drivers/i2c/busses/i2c-designware-master.c    | 23 +++++++++++++++++--
 4 files changed, 50 insertions(+), 2 deletions(-)

Comments

Michael Wu Oct. 28, 2024, 5:24 a.m. UTC | #1
On 03.10.23, Michael Wu wrote:
> In commit 35eba185fd1a ("i2c: designware: Calculate SCL timing parameter
> for High Speed Mode") the SCL high period count and low period count for
> high speed mode are calculated based on fixed tHIGH = 160 and tLOW = 120.
> However, the set of two fixed values is only applicable to the combination
> of hardware parameters IC_CAP_LOADING is 400 and
> IC_CLK_FREQ_OPTIMIZATION
> is true. Outside of this combination, the SCL frequency may not reach
> 3.4 MHz because the fixed tHIGH and tLOW are not small enough.
> 
> Since there are no any registers controlling these two hardware parameters,
> their values can only be declared through the device tree.
> 
> v4:
> - yaml: re-formatting two properties' description
> - yaml: enumeriate bus-capacitance-pf
> - yaml: extand an existing example
> - driver: modify the commit description
> - driver: rename "bus-capacitance-pf" to "bus-capacitance-pF"
> 
> v3:
> - add vendor prefix on new property name
> - read new properties in i2c_dw_fw_parse_and_configure() directly
> - in i2c_dw_set_timings_master() check dev->bus_capacitance_pf and then
> decide
>   t_high and t_low
> 
> v2:
> - provide more hardware information in dt-bindings
> - rename "bus-loading" to "bus-capacitance-pf"
> - call new i2c_dw_fw_parse_hw_params() in i2c_dw_fw_parse_and_configure()
> to
>   parse hardware parameters from the device tree.
> 
> Michael Wu (2):
>   dt-bindings: i2c: snps,designware-i2c: declare bus capacitance and clk
>     freq optimized
>   i2c: dwsignware: determine HS tHIGH and tLOW based on HW parameters
> 
>  .../bindings/i2c/snps,designware-i2c.yaml     | 18 +++++++++++++++
>  drivers/i2c/busses/i2c-designware-common.c    |  5 ++++
>  drivers/i2c/busses/i2c-designware-core.h      |  6 +++++
>  drivers/i2c/busses/i2c-designware-master.c    | 23 +++++++++++++++++--
>  4 files changed, 50 insertions(+), 2 deletions(-)
> 
> --
> 2.43.0

Hi Andi,

Please forgive me for my presumption. Regarding this patch, will it be
merged? If not, please kindly provide any suggestions I can make to
improve it.

Sincerely yours,
Michael Wu
Andi Shyti Nov. 19, 2024, 10:58 p.m. UTC | #2
Hi Michael,

> Michael Wu (2):
>   dt-bindings: i2c: snps,designware-i2c: declare bus capacitance and clk
>     freq optimized
>   i2c: dwsignware: determine HS tHIGH and tLOW based on HW parameters

merged to i2c/i2c-host.

Thanks,
Andi