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[0/6] i2c: designware: Generic polling mode code

Message ID 20240131141653.2689260-1-jarkko.nikula@linux.intel.com
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Series i2c: designware: Generic polling mode code | expand

Message

Jarkko Nikula Jan. 31, 2024, 2:16 p.m. UTC
Hi Jiawen, Sanket and Basavaraj

Could you test on your Wangxun 10Gb NIC and AMD NAVI GPU harware this
patchset since it's touching both.

For the AMD NAVI GPU and changes are less but for the Wangxun 10Gb NIC
patchset replaces the txgbe_i2c_dw_xfer_quirk() with generic polling mode
code.

I've been testing this on our HW which all have interrupt connected and
tried to cover also FIFO depth defines for Wangxun 10Gb NIC. Obviously I
would like to know how this set works on your real HW.

Jarkko Nikula (6):
  i2c: designware: Uniform initialization flow for polling mode
  i2c: designware: Do not enable interrupts shortly in polling mode
  i2c: designware: Use accessors to DW_IC_INTR_MASK register
  i2c: designware: Move interrupt handling functions before
    i2c_dw_xfer()
  i2c: designware: Fix RX FIFO depth define on Wangxun 10Gb NIC
  i2c: designware: Implement generic polling mode code for Wangxun 10Gb
    NIC

 drivers/i2c/busses/i2c-designware-common.c  |   2 +-
 drivers/i2c/busses/i2c-designware-core.h    |  23 +-
 drivers/i2c/busses/i2c-designware-master.c  | 417 +++++++++-----------
 drivers/i2c/busses/i2c-designware-pcidrv.c  |   2 +-
 drivers/i2c/busses/i2c-designware-platdrv.c |   2 +-
 5 files changed, 208 insertions(+), 238 deletions(-)

Comments

Jiawen Wu Feb. 4, 2024, 3:20 a.m. UTC | #1
On Wed, Jan 31, 2024 10:17 PM, Jarkko Nikula wrote:
> Hi Jiawen, Sanket and Basavaraj
> 
> Could you test on your Wangxun 10Gb NIC and AMD NAVI GPU harware this
> patchset since it's touching both.
> 
> For the AMD NAVI GPU and changes are less but for the Wangxun 10Gb NIC
> patchset replaces the txgbe_i2c_dw_xfer_quirk() with generic polling mode
> code.
> 
> I've been testing this on our HW which all have interrupt connected and
> tried to cover also FIFO depth defines for Wangxun 10Gb NIC. Obviously I
> would like to know how this set works on your real HW.

Hi Jarkko,

Sorry for the late reply.
I've been testing the patch series on Wangxun 10Gb NIC, it works well.
Thanks!
Jarkko Nikula Feb. 5, 2024, 7:30 a.m. UTC | #2
Hi

On 2/4/24 05:20, Jiawen Wu wrote:
> On Wed, Jan 31, 2024 10:17 PM, Jarkko Nikula wrote:
>> I've been testing this on our HW which all have interrupt connected and
>> tried to cover also FIFO depth defines for Wangxun 10Gb NIC. Obviously I
>> would like to know how this set works on your real HW.
> 
> Hi Jarkko,
> 
> Sorry for the late reply.
> I've been testing the patch series on Wangxun 10Gb NIC, it works well.
> Thanks!
> 
Thank you very much! The first priority for this set it must not cause a 
regression on your HW and I'm glad my idea works :-)