| Message ID | 20211217093325.30612-1-conor.dooley@microchip.com |
|---|---|
| Headers | show |
| Series | Update the Icicle Kit device tree | expand |
Hi Conor, Thanks for your patch! On Fri, Dec 17, 2021 at 10:33 AM <conor.dooley@microchip.com> wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Update the Microchip Icicle kit device tree by replacing interrupt and > clock related magic numbers with their defined counterparts. Usually we make a distinction between (a) numbers that can be looked up easily in a datasheet, and (b) numbers that were made up because we needed some mapping. Of course both types of numbers are fixed, and cannot be changed. For (a), we tend to use the hardcoded numbers in the DTS files, to avoid reviewers having to go through another layer of indirection (i.e. does the number for the define match the number in the datasheet?). For (b), we use the defines, as there is no other official place to look up the numbers. > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > @@ -2,6 +2,8 @@ > /* Copyright (c) 2020 Microchip Technology Inc */ > > /dts-v1/; > +#include "dt-bindings/clock/microchip,mpfs-clock.h" The clock numbers we're made-up, so they fall under (b). > +#include "dt-bindings/interrupt-controller/riscv-hart.h" I believe these are just the official CLIC interrupt IDs, so they fall under (a)? > @@ -165,11 +167,16 @@ cache-controller@2010000 { > clint@2000000 { > compatible = "sifive,fu540-c000-clint", "sifive,clint0"; > reg = <0x0 0x2000000 0x0 0xC000>; > - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > - <&cpu1_intc 3>, <&cpu1_intc 7>, > - <&cpu2_intc 3>, <&cpu2_intc 7>, > - <&cpu3_intc 3>, <&cpu3_intc 7>, > - <&cpu4_intc 3>, <&cpu4_intc 7>; > + interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>, > + <&cpu0_intc HART_INT_M_TIMER>, > + <&cpu1_intc HART_INT_M_SOFT>, > + <&cpu1_intc HART_INT_M_TIMER>, > + <&cpu2_intc HART_INT_M_SOFT>, > + <&cpu2_intc HART_INT_M_TIMER>, > + <&cpu3_intc HART_INT_M_SOFT>, > + <&cpu3_intc HART_INT_M_TIMER>, > + <&cpu4_intc HART_INT_M_SOFT>, > + <&cpu4_intc HART_INT_M_TIMER>; Hence I'm not sure we want changes like this? > }; > > plic: interrupt-controller@c000000 { }; > > @@ -210,7 +221,7 @@ serial0: serial@20000000 { > interrupt-parent = <&plic>; > interrupts = <90>; > current-speed = <115200>; > - clocks = <&clkcfg 8>; > + clocks = <&clkcfg CLK_MMUART0>; But this change is fine. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Fri, 17 Dec 2021 09:33:19 +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add device tree bindings for the usb controller on > the Microchip PolarFire SoC. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/usb/microchip,mpfs-musb.yaml | 61 +++++++++++++++++++ > 1 file changed, 61 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory 19 | #include "dt-bindings/clock/microchip,mpfs-clock.h" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1413: dt_binding_check] Error 2 doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/1569849 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On 17/12/2021 10:33, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Assorted minor changes to the MPFS/Icicle kit device tree: > > - rename serial to mmuart to match microchip documentation > - enable mmuart4 instead of mmuart0 This is not refactoring. Refactoring could include renames, hierarchy/layout differences, naming, coding convention. You are changing features, e.g. using different UART. Please split the changes. > - move stdout path to serial1 to avoid collision with > bootloader running on the e51 > - split memory node to match updated fpga design > - move phy0 inside mac1 node to match phy configuration > - add labels where missing (cpus, cache controller) > - add missing address cells & interrupts to MACs > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../microchip/microchip-mpfs-icicle-kit.dts | 52 ++++++++------ > .../boot/dts/microchip/microchip-mpfs.dtsi | 70 ++++++++++--------- > 2 files changed, 68 insertions(+), 54 deletions(-) > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > index 174f977c164b..f6542ef76046 100644 > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > @@ -1,5 +1,5 @@ > // SPDX-License-Identifier: (GPL-2.0 OR MIT) > -/* Copyright (c) 2020 Microchip Technology Inc */ > +/* Copyright (c) 2020-2021 Microchip Technology Inc */ > > /dts-v1/; > > @@ -13,25 +13,34 @@ / { > compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; > > aliases { > - ethernet0 = &emac1; > - serial0 = &serial0; > - serial1 = &serial1; > - serial2 = &serial2; > - serial3 = &serial3; > + ethernet0 = &mac1; > + serial0 = &mmuart0; > + serial1 = &mmuart1; > + serial2 = &mmuart2; > + serial3 = &mmuart3; > + serial4 = &mmuart4; > }; > > chosen { > - stdout-path = "serial0:115200n8"; > + stdout-path = "serial1:115200n8"; > }; > > cpus { > timebase-frequency = <RTCCLK_FREQ>; > }; > > - memory@80000000 { > + ddrc_cache_lo: memory@80000000 { > device_type = "memory"; > - reg = <0x0 0x80000000 0x0 0x40000000>; > + reg = <0x0 0x80000000 0x0 0x2e000000>; > clocks = <&clkcfg CLK_DDRC>; > + status = "okay"; > + }; > + > + ddrc_cache_hi: memory@1000000000 { This looks unrelated to refactoring - split of memory - and needs separate change. > + device_type = "memory"; > + reg = <0x10 0x0 0x0 0x40000000>; > + clocks = <&clkcfg CLK_DDRC>; > + status = "okay"; > }; > }; > > @@ -39,19 +48,19 @@ &refclk { > clock-frequency = <600000000>; > }; > > -&serial0 { > +&mmuart1 { > status = "okay"; > }; > > -&serial1 { > +&mmuart2 { > status = "okay"; > }; > > -&serial2 { > +&mmuart3 { > status = "okay"; > }; > > -&serial3 { > +&mmuart4 { > status = "okay"; > }; > > @@ -61,29 +70,32 @@ &mmc { > bus-width = <4>; > disable-wp; > cap-sd-highspeed; > + cap-mmc-highspeed; > card-detect-delay = <200>; > + mmc-ddr-1_8v; > + mmc-hs200-1_8v; This looks unrelated to refactoring - new modes for MMC - and needs separate change. > sd-uhs-sdr12; > sd-uhs-sdr25; > sd-uhs-sdr50; > sd-uhs-sdr104; > }; > > -&emac0 { > +&mac0 { > phy-mode = "sgmii"; > phy-handle = <&phy0>; > - phy0: ethernet-phy@8 { > - reg = <8>; > - ti,fifo-depth = <0x01>; > - }; > }; > > -&emac1 { > +&mac1 { > status = "okay"; > phy-mode = "sgmii"; > phy-handle = <&phy1>; > phy1: ethernet-phy@9 { > reg = <9>; > - ti,fifo-depth = <0x01>; > + ti,fifo-depth = <0x1>; > + }; > + phy0: ethernet-phy@8 { > + reg = <8>; > + ti,fifo-depth = <0x1>; > }; > }; > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > index 808500be26c3..d311c5ea27c9 100644 > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > @@ -1,5 +1,5 @@ > // SPDX-License-Identifier: (GPL-2.0 OR MIT) > -/* Copyright (c) 2020 Microchip Technology Inc */ > +/* Copyright (c) 2020-2021 Microchip Technology Inc */ > > /dts-v1/; > #include "dt-bindings/clock/microchip,mpfs-clock.h" > @@ -16,7 +16,7 @@ cpus { > #address-cells = <1>; > #size-cells = <0>; > > - cpu@0 { > + cpu0: cpu@0 { > compatible = "sifive,e51", "sifive,rocket0", "riscv"; > device_type = "cpu"; > i-cache-block-size = <64>; > @@ -34,7 +34,7 @@ cpu0_intc: interrupt-controller { > }; > }; > > - cpu@1 { > + cpu1: cpu@1 { > compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > d-cache-block-size = <64>; > d-cache-sets = <64>; > @@ -61,7 +61,7 @@ cpu1_intc: interrupt-controller { > }; > }; > > - cpu@2 { > + cpu2: cpu@2 { > compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > d-cache-block-size = <64>; > d-cache-sets = <64>; > @@ -88,7 +88,7 @@ cpu2_intc: interrupt-controller { > }; > }; > > - cpu@3 { > + cpu3: cpu@3 { > compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > d-cache-block-size = <64>; > d-cache-sets = <64>; > @@ -115,7 +115,7 @@ cpu3_intc: interrupt-controller { > }; > }; > > - cpu@4 { > + cpu4: cpu@4 { > compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > d-cache-block-size = <64>; > d-cache-sets = <64>; > @@ -153,8 +153,9 @@ soc { > compatible = "simple-bus"; > ranges; > > - cache-controller@2010000 { > + cctrllr: cache-controller@2010000 { > compatible = "sifive,fu540-c000-ccache", "cache"; > + reg = <0x0 0x2010000 0x0 0x1000>; > cache-block-size = <64>; > cache-level = <2>; > cache-sets = <1024>; > @@ -162,10 +163,9 @@ cache-controller@2010000 { > cache-unified; > interrupt-parent = <&plic>; > interrupts = <1>, <2>, <3>; > - reg = <0x0 0x2010000 0x0 0x1000>; > }; > > - clint@2000000 { > + clint: clint@2000000 { > compatible = "sifive,fu540-c000-clint", "sifive,clint0"; > reg = <0x0 0x2000000 0x0 0xC000>; > interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>, > @@ -198,15 +198,6 @@ plic: interrupt-controller@c000000 { > riscv,ndev = <186>; > }; > > - dma@3000000 { > - compatible = "sifive,fu540-c000-pdma"; Removal of nodes does not look like refactoring. > - reg = <0x0 0x3000000 0x0 0x8000>; > - interrupt-parent = <&plic>; > - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, > - <30>; > - #dma-cells = <1>; > - }; > - Best regards, Krzysztof
On 17/12/2021 10:33, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Update the RISC-V/Microchip entry by adding the microchip dts > directory and myself as maintainer > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > MAINTAINERS | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 7a2345ce8521..3b1d6be7bd56 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -16348,8 +16348,10 @@ K: riscv > > RISC-V/MICROCHIP POLARFIRE SOC SUPPORT > M: Lewis Hanly <lewis.hanly@microchip.com> > +M: Conor Dooley <conor.dooley@microchip.com> > L: linux-riscv@lists.infradead.org > S: Supported > +F: arch/riscv/boot/dts/microchip/ > F: drivers/mailbox/mailbox-mpfs.c > F: drivers/soc/microchip/ > F: include/soc/microchip/mpfs.h > Good to have the DTS covered, so FWIW: Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> You still should get Lewis' ack (unless he merges it) Best regards, Krzysztof
On 17/12/2021 15:04, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 17/12/2021 10:33, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Assorted minor changes to the MPFS/Icicle kit device tree: >> >> - rename serial to mmuart to match microchip documentation >> - enable mmuart4 instead of mmuart0 > > This is not refactoring. Refactoring could include renames, > hierarchy/layout differences, naming, coding convention. You are > changing features, e.g. using different UART. Please split the changes. will do :) > >> - move stdout path to serial1 to avoid collision with >> bootloader running on the e51 >> - split memory node to match updated fpga design >> - move phy0 inside mac1 node to match phy configuration >> - add labels where missing (cpus, cache controller) >> - add missing address cells & interrupts to MACs >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> .../microchip/microchip-mpfs-icicle-kit.dts | 52 ++++++++------ >> .../boot/dts/microchip/microchip-mpfs.dtsi | 70 ++++++++++--------- >> 2 files changed, 68 insertions(+), 54 deletions(-) >> >> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts >> index 174f977c164b..f6542ef76046 100644 >> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts >> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts >> @@ -1,5 +1,5 @@ >> // SPDX-License-Identifier: (GPL-2.0 OR MIT) >> -/* Copyright (c) 2020 Microchip Technology Inc */ >> +/* Copyright (c) 2020-2021 Microchip Technology Inc */ >> >> /dts-v1/; >> >> @@ -13,25 +13,34 @@ / { >> compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; >> >> aliases { >> - ethernet0 = &emac1; >> - serial0 = &serial0; >> - serial1 = &serial1; >> - serial2 = &serial2; >> - serial3 = &serial3; >> + ethernet0 = &mac1; >> + serial0 = &mmuart0; >> + serial1 = &mmuart1; >> + serial2 = &mmuart2; >> + serial3 = &mmuart3; >> + serial4 = &mmuart4; >> }; >> >> chosen { >> - stdout-path = "serial0:115200n8"; >> + stdout-path = "serial1:115200n8"; >> }; >> >> cpus { >> timebase-frequency = <RTCCLK_FREQ>; >> }; >> >> - memory@80000000 { >> + ddrc_cache_lo: memory@80000000 { >> device_type = "memory"; >> - reg = <0x0 0x80000000 0x0 0x40000000>; >> + reg = <0x0 0x80000000 0x0 0x2e000000>; >> clocks = <&clkcfg CLK_DDRC>; >> + status = "okay"; >> + }; >> + >> + ddrc_cache_hi: memory@1000000000 { > > This looks unrelated to refactoring - split of memory - and needs > separate change. > >> + device_type = "memory"; >> + reg = <0x10 0x0 0x0 0x40000000>; >> + clocks = <&clkcfg CLK_DDRC>; >> + status = "okay"; >> }; >> }; >> >> @@ -39,19 +48,19 @@ &refclk { >> clock-frequency = <600000000>; >> }; >> >> -&serial0 { >> +&mmuart1 { >> status = "okay"; >> }; >> >> -&serial1 { >> +&mmuart2 { >> status = "okay"; >> }; >> >> -&serial2 { >> +&mmuart3 { >> status = "okay"; >> }; >> >> -&serial3 { >> +&mmuart4 { >> status = "okay"; >> }; >> >> @@ -61,29 +70,32 @@ &mmc { >> bus-width = <4>; >> disable-wp; >> cap-sd-highspeed; >> + cap-mmc-highspeed; >> card-detect-delay = <200>; >> + mmc-ddr-1_8v; >> + mmc-hs200-1_8v; > > This looks unrelated to refactoring - new modes for MMC - and needs > separate change. > >> sd-uhs-sdr12; >> sd-uhs-sdr25; >> sd-uhs-sdr50; >> sd-uhs-sdr104; >> }; >> >> -&emac0 { >> +&mac0 { >> phy-mode = "sgmii"; >> phy-handle = <&phy0>; >> - phy0: ethernet-phy@8 { >> - reg = <8>; >> - ti,fifo-depth = <0x01>; >> - }; >> }; >> >> -&emac1 { >> +&mac1 { >> status = "okay"; >> phy-mode = "sgmii"; >> phy-handle = <&phy1>; >> phy1: ethernet-phy@9 { >> reg = <9>; >> - ti,fifo-depth = <0x01>; >> + ti,fifo-depth = <0x1>; >> + }; >> + phy0: ethernet-phy@8 { >> + reg = <8>; >> + ti,fifo-depth = <0x1>; >> }; >> }; >> >> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi >> index 808500be26c3..d311c5ea27c9 100644 >> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi >> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi >> @@ -1,5 +1,5 @@ >> // SPDX-License-Identifier: (GPL-2.0 OR MIT) >> -/* Copyright (c) 2020 Microchip Technology Inc */ >> +/* Copyright (c) 2020-2021 Microchip Technology Inc */ >> >> /dts-v1/; >> #include "dt-bindings/clock/microchip,mpfs-clock.h" >> @@ -16,7 +16,7 @@ cpus { >> #address-cells = <1>; >> #size-cells = <0>; >> >> - cpu@0 { >> + cpu0: cpu@0 { >> compatible = "sifive,e51", "sifive,rocket0", "riscv"; >> device_type = "cpu"; >> i-cache-block-size = <64>; >> @@ -34,7 +34,7 @@ cpu0_intc: interrupt-controller { >> }; >> }; >> >> - cpu@1 { >> + cpu1: cpu@1 { >> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; >> d-cache-block-size = <64>; >> d-cache-sets = <64>; >> @@ -61,7 +61,7 @@ cpu1_intc: interrupt-controller { >> }; >> }; >> >> - cpu@2 { >> + cpu2: cpu@2 { >> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; >> d-cache-block-size = <64>; >> d-cache-sets = <64>; >> @@ -88,7 +88,7 @@ cpu2_intc: interrupt-controller { >> }; >> }; >> >> - cpu@3 { >> + cpu3: cpu@3 { >> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; >> d-cache-block-size = <64>; >> d-cache-sets = <64>; >> @@ -115,7 +115,7 @@ cpu3_intc: interrupt-controller { >> }; >> }; >> >> - cpu@4 { >> + cpu4: cpu@4 { >> compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; >> d-cache-block-size = <64>; >> d-cache-sets = <64>; >> @@ -153,8 +153,9 @@ soc { >> compatible = "simple-bus"; >> ranges; >> >> - cache-controller@2010000 { >> + cctrllr: cache-controller@2010000 { >> compatible = "sifive,fu540-c000-ccache", "cache"; >> + reg = <0x0 0x2010000 0x0 0x1000>; >> cache-block-size = <64>; >> cache-level = <2>; >> cache-sets = <1024>; >> @@ -162,10 +163,9 @@ cache-controller@2010000 { >> cache-unified; >> interrupt-parent = <&plic>; >> interrupts = <1>, <2>, <3>; >> - reg = <0x0 0x2010000 0x0 0x1000>; >> }; >> >> - clint@2000000 { >> + clint: clint@2000000 { >> compatible = "sifive,fu540-c000-clint", "sifive,clint0"; >> reg = <0x0 0x2000000 0x0 0xC000>; >> interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>, >> @@ -198,15 +198,6 @@ plic: interrupt-controller@c000000 { >> riscv,ndev = <186>; >> }; >> >> - dma@3000000 { >> - compatible = "sifive,fu540-c000-pdma"; > > Removal of nodes does not look like refactoring. > >> - reg = <0x0 0x3000000 0x0 0x8000>; >> - interrupt-parent = <&plic>; >> - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, >> - <30>; >> - #dma-cells = <1>; >> - }; >> - > > > Best regards, > Krzysztof >
On 17/12/2021 16:22, Conor.Dooley@microchip.com wrote: > On 17/12/2021 15:07, Krzysztof Kozlowski wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> On 17/12/2021 15:53, Krzysztof Kozlowski wrote: >>> On 17/12/2021 10:33, conor.dooley@microchip.com wrote: >>>> From: Conor Dooley <conor.dooley@microchip.com> >>>> >>>> Add device tree bindings for the hardware rng device accessed via >>>> the system services on the Microchip PolarFire SoC. >>>> >>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >>>> --- >>>> .../bindings/rng/microchip,mpfs-rng.yaml | 29 +++++++++++++++++++ >>>> 1 file changed, 29 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml >>>> >>>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml >>>> new file mode 100644 >>>> index 000000000000..32cbc37c9292 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml >>>> @@ -0,0 +1,29 @@ >>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>> +%YAML 1.2 >>>> +--- >>>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#" >>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#" >>>> + >>>> +title: Microchip MPFS random number generator >>>> + >>>> +maintainers: >>>> + - Conor Dooley <conor.dooley@microchip.com> >>>> + >>>> +description: | >>>> + The hardware random number generator on the Polarfire SoC is >>>> + accessed via the mailbox interface provided by the system controller >>>> + >>>> +properties: >>>> + compatible: >>>> + const: microchip,mpfs-rng >>>> + >>>> +required: >>>> + - compatible >>>> + >>>> +additionalProperties: false >>>> + >>>> +examples: >>>> + - | >>>> + hwrandom: hwrandom { >>> >>> Three topics: >>> 1. Node name (as most of others are using): rng >>> 2. skip the label, not helping in example. >>> 3. This looks very simple, so I wonder if the bindings are complete. No >>> IO space/address... How is it going to be instantiated? >>> >> >> OK, now I saw the usage in DTS. I have doubts this makes sense as >> separate bindings. It looks like integrated part of syscontroller, so >> maybe make it part of that binding? Or at least add ref to syscontroller >> bindings that such child is expected. > Acking the rest of this, re: adding the ref: is what is being done in > patch 03/17 insufficient? Ops, I missed the 03/17. Yeah, it looks it is sufficient and in such case I think you do not need this patch. The compatible is documented in 03/17. The same for sysserv. Best regards, Krzysztof
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Friday, December 17th, 2021 at 15:47, Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> wrote: > On 17/12/2021 16:22, Conor.Dooley@microchip.com wrote: > > > On 17/12/2021 15:07, Krzysztof Kozlowski wrote: > > > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > > > On 17/12/2021 15:53, Krzysztof Kozlowski wrote: > > > > > > > On 17/12/2021 10:33, conor.dooley@microchip.com wrote: > > > > > > > > > From: Conor Dooley conor.dooley@microchip.com > > > > > > > > > > Add device tree bindings for the hardware rng device accessed via > > > > > > > > > > the system services on the Microchip PolarFire SoC. > > > > > > > > > > Signed-off-by: Conor Dooley conor.dooley@microchip.com > > > > > ------------------------------------------------------ > > > > > > > > Three topics: > > > > > > > > 1. Node name (as most of others are using): rng > > > > 2. skip the label, not helping in example. > > > > 3. This looks very simple, so I wonder if the bindings are complete. No > > > > > > > > IO space/address... How is it going to be instantiated? > > > OK, now I saw the usage in DTS. I have doubts this makes sense as > > > separate bindings. It looks like integrated part of syscontroller, so > > > maybe make it part of that binding? Or at least add ref to syscontroller > > > bindings that such child is expected. > > Acking the rest of this, re: adding the ref: is what is being done in > > patch 03/17 insufficient? > Ops, I missed the 03/17. Yeah, it looks it is sufficient and in such > case I think you do not need this patch. The compatible is documented in > 03/17. The same for sysserv. Grand, that makes things easier. Conor. > > Best regards, > > Krzysztof > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 17/12/2021 15:09, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 17/12/2021 10:33, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Update the RISC-V/Microchip entry by adding the microchip dts >> directory and myself as maintainer >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> MAINTAINERS | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 7a2345ce8521..3b1d6be7bd56 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -16348,8 +16348,10 @@ K: riscv >> >> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT >> M: Lewis Hanly <lewis.hanly@microchip.com> >> +M: Conor Dooley <conor.dooley@microchip.com> >> L: linux-riscv@lists.infradead.org >> S: Supported >> +F: arch/riscv/boot/dts/microchip/ >> F: drivers/mailbox/mailbox-mpfs.c >> F: drivers/soc/microchip/ >> F: include/soc/microchip/mpfs.h >> > > Good to have the DTS covered, so FWIW: > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > > You still should get Lewis' ack (unless he merges it) Aye, it'll be an ack. We don't currently have a tree & would rather do this via risc-v than the at91/sam arm soc tree. > > Best regards, > Krzysztof >
On Thu, 23 Dec 2021 06:56:45 PST (-0800), Conor.Dooley@microchip.com wrote: > On 17/12/2021 15:09, Krzysztof Kozlowski wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> On 17/12/2021 10:33, conor.dooley@microchip.com wrote: >>> From: Conor Dooley <conor.dooley@microchip.com> >>> >>> Update the RISC-V/Microchip entry by adding the microchip dts >>> directory and myself as maintainer >>> >>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >>> --- >>> MAINTAINERS | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/MAINTAINERS b/MAINTAINERS >>> index 7a2345ce8521..3b1d6be7bd56 100644 >>> --- a/MAINTAINERS >>> +++ b/MAINTAINERS >>> @@ -16348,8 +16348,10 @@ K: riscv >>> >>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT >>> M: Lewis Hanly <lewis.hanly@microchip.com> >>> +M: Conor Dooley <conor.dooley@microchip.com> >>> L: linux-riscv@lists.infradead.org >>> S: Supported >>> +F: arch/riscv/boot/dts/microchip/ >>> F: drivers/mailbox/mailbox-mpfs.c >>> F: drivers/soc/microchip/ >>> F: include/soc/microchip/mpfs.h >>> >> >> Good to have the DTS covered, so FWIW: >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> >> >> You still should get Lewis' ack (unless he merges it) > Aye, it'll be an ack. We don't currently have a tree & would rather do > this via risc-v than the at91/sam arm soc tree. WFM. I'll be awaiting the ack. I don't see any fundamental issues from my end, as long is it's got all the acks/reviews then I'm generally fine with this sort of stuff. I'll take a look before merging it, I'm kind of buried right now. Sorry! >> >> Best regards, >> Krzysztof >> >
On 17/12/2021 15:09, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know > the content is safe > > On 17/12/2021 10:33, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Update the RISC-V/Microchip entry by adding the microchip dts >> directory and myself as maintainer >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Lewis Hanly <lewis.hanly@microchip.com> >> --- >> MAINTAINERS | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS index >> 7a2345ce8521..3b1d6be7bd56 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -16348,8 +16348,10 @@ K: riscv >> >> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT >> M: Lewis Hanly <lewis.hanly@microchip.com> >> +M: Conor Dooley <conor.dooley@microchip.com> >> L: linux-riscv@lists.infradead.org >> S: Supported >> +F: arch/riscv/boot/dts/microchip/ >> F: drivers/mailbox/mailbox-mpfs.c >> F: drivers/soc/microchip/ >> F: include/soc/microchip/mpfs.h >> > > Good to have the DTS covered, so FWIW: > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > > You still should get Lewis' ack (unless he merges it) Aye, it'll be an ack. We don't currently have a tree & would rather do this via risc-v than the at91/sam arm soc tree. > > Best regards, > Krzysztof >
From: Conor Dooley <conor.dooley@microchip.com> This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric. Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid as many "DT compatible string <x> appears un-documented" errors as possible. Depends on mpfs clock driver series [1] to provide: dt-bindings/clock/microchip,mpfs-clock.h and on the other changes to the icicle/mpfs device tree (mmc) that are already in linux/riscv/for-next. Also depends on Geert's format changes to interrupt grouping etc [2]. Additionally, the interrupt-extended warnings on the plic/clint are cleared by [3] & [4], which lore appears to have been very confused about. [1] https://lore.kernel.org/linux-clk/20211216140022.16146-1-conor.dooley@microchip.com/T/ [2] https://lore.kernel.org/linux-riscv/cover.1639660956.git.geert@linux-m68k.org/T/ [3] https://patchwork.kernel.org/project/linux-riscv/cover/cover.1639662093.git.geert@linux-m68k.org/ [4] https://patchwork.kernel.org/project/linux-riscv/cover/cover.1639661878.git.geert@linux-m68k.org/ Conor Dooley (16): dt-bindings: soc/microchip: update syscontroller compatibles dt-bindings: soc/microchip: make systemcontroller a mfd mailbox: change mailbox-mpfs compatible string dt-bindings: i2c: add bindings for microchip mpfs i2c dt-bindings: rng: add bindings for microchip mpfs rng dt-bindings: rtc: add bindings for microchip mpfs rtc dt-bindings: soc/microchip: add bindings for mpfs system services dt-bindings: gpio: add bindings for microchip mpfs gpio dt-bindings: spi: add bindings for microchip mpfs spi dt-bindings: usb: add bindings for microchip mpfs musb dt-bindings: pwm: add microchip corePWM binding riscv: dts: microchip: use hart and clk defines for icicle kit riscv: dts: microchip: add fpga fabric section to icicle kit riscv: dts: microchip: refactor icicle kit device tree riscv: dts: microchip: update peripherals in icicle kit device tree MAINTAINERS: update riscv/microchip entry Ivan Griffin (1): dt-bindings: interrupt-controller: create a header for RISC-V interrupts .../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++ .../bindings/i2c/microchip,mpfs-i2c.yaml | 54 ++++ ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +- .../bindings/pwm/microchip,corepwm.yaml | 61 ++++ .../bindings/rng/microchip,mpfs-rng.yaml | 29 ++ .../bindings/rtc/microchip,mfps-rtc.yaml | 63 ++++ .../microchip,mpfs-generic-service.yaml | 33 ++ .../microchip,mpfs-sys-controller.yaml | 62 ++++ ...icrochip,polarfire-soc-sys-controller.yaml | 35 --- .../bindings/spi/microchip,mpfs-spi.yaml | 61 ++++ .../bindings/usb/microchip,mpfs-musb.yaml | 61 ++++ MAINTAINERS | 2 + .../dts/microchip/microchip-mpfs-fabric.dtsi | 13 + .../microchip/microchip-mpfs-icicle-kit.dts | 111 +++++-- .../boot/dts/microchip/microchip-mpfs.dtsi | 295 ++++++++++++++---- drivers/mailbox/mailbox-mpfs.c | 2 +- .../interrupt-controller/riscv-hart.h | 19 ++ 17 files changed, 872 insertions(+), 115 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h