| Message ID | 1607403341-57214-1-git-send-email-yash.shah@sifive.com |
|---|---|
| Headers | show |
| Series | arch: riscv: add board and SoC DT file support | expand |
On Tue, 8 Dec 2020 10:25:32 +0530, Yash Shah wrote: > Start board support by adding initial support for the SiFive FU740 SoC > and the first development board that uses it, the SiFive HiFive > Unmatched A00. > > Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the > U-boot and OpenSBI. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [2/9] dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC commit: 76347344c522da78be29403dda81463ffae2bc99 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
On Tue, 08 Dec 2020 10:25:33 +0530, Yash Shah wrote: > Add new compatible strings in cpus.yaml to support the E71 and U74 CPU > cores ("harts") that are present on FU740-C000 SoC. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
On Tue, Dec 08, 2020 at 10:25:35AM +0530, Yash Shah wrote: > Add new compatible strings to the DT binding documents to support SiFive > FU740-C000. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > index 5ac2527..84e6691 100644 > --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml > @@ -25,12 +25,15 @@ description: > properties: > compatible: > items: > - - const: sifive,fu540-c000-pwm > + - enum: > + - sifive,fu540-c000-pwm > + - sifive,fu740-c000-pwm > - const: sifive,pwm0 > description: > Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported > - compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0 > - as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the > + compatible strings are "sifive,fu540-c000-pwm" and > + "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the > + SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the Better if you reword this so we don't have to update it for every new compatible. > SiFive PWM v0 IP block with no chip integration tweaks. > Please refer to sifive-blocks-ip-versioning.txt for details. > > -- > 2.7.4 >
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > Add new compatible strings in cpus.yaml to support the E71 and U74 CPU > cores ("harts") that are present on FU740-C000 SoC. > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Bin Meng <bin.meng@windriver.com>
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > Add initial board data for the SiFive HiFive Unmatched A00. > This patch is dependent on Zong's Patchset[0]. > > [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u I think the dependency should be put below --, not in the commit message itself > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > --- > arch/riscv/boot/dts/sifive/Makefile | 3 +- > .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +++++++++++++++++++++ > 2 files changed, 255 insertions(+), 1 deletion(-) > create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts > > diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile > index 6d6189e..74c47fe 100644 > --- a/arch/riscv/boot/dts/sifive/Makefile > +++ b/arch/riscv/boot/dts/sifive/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0 > -dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb > +dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \ > + hifive-unmatched-a00.dtb Otherwise LGTM: Reviewed-by: Bin Meng <bin.meng@windriver.com>
> -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 10 December 2020 19:05 > To: Yash Shah <yash.shah@openfive.com> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > C000 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > > FU740-C000 Soc > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > This file is expected to grow as more device drivers are added to the > > kernel. > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > --- > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > +++++++++++++++++++++++++++++ > > 1 file changed, 293 insertions(+) > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > new file mode 100644 > > index 0000000..eeb4f8c3 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > @@ -0,0 +1,293 @@ ... > > + plic0: interrupt-controller@c000000 { > > + #interrupt-cells = <1>; > > + #address-cells = <0>; > > + compatible = "sifive,fu540-c000-plic", > > + "sifive,plic-1.0.0"; > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? That's because it is not required. There won't be any difference in driver code for FU740 plic. ... > > + eth0: ethernet@10090000 { > > + compatible = "sifive,fu540-c000-gem"; > > "sifive,fu740-c000-gem"? > Same reason as above. Thanks for your review. - Yash > > + interrupt-parent = <&plic0>; > > + interrupts = <55>; > > + reg = <0x0 0x10090000 0x0 0x2000>, > > + <0x0 0x100a0000 0x0 0x1000>; > > + local-mac-address = [00 00 00 00 00 00]; > > + clock-names = "pclk", "hclk"; > > + clocks = <&prci PRCI_CLK_GEMGXLPLL>, > > + <&prci PRCI_CLK_GEMGXLPLL>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + status = "disabled"; > > + }; > > + pwm0: pwm@10020000 { > > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; > > + reg = <0x0 0x10020000 0x0 0x1000>; > > + interrupt-parent = <&plic0>; > > + interrupts = <44>, <45>, <46>, <47>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + pwm1: pwm@10021000 { > > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; > > + reg = <0x0 0x10021000 0x0 0x1000>; > > + interrupt-parent = <&plic0>; > > + interrupts = <48>, <49>, <50>, <51>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + #pwm-cells = <3>; > > + status = "disabled"; > > + }; > > + ccache: cache-controller@2010000 { > > + compatible = "sifive,fu740-c000-ccache", "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <2048>; > > + cache-size = <2097152>; > > + cache-unified; > > + interrupt-parent = <&plic0>; > > + interrupts = <19 20 21 22>; > > + reg = <0x0 0x2010000 0x0 0x1000>; > > + }; > > + gpio: gpio@10060000 { > > + compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; > > + interrupt-parent = <&plic0>; > > + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, > > + <30>, <31>, <32>, <33>, <34>, <35>, <36>, > > + <37>, <38>; > > + reg = <0x0 0x10060000 0x0 0x1000>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + clocks = <&prci PRCI_CLK_PCLK>; > > + status = "disabled"; > > + }; > > + }; > > +}; > > Regards, > Bin
Hi Yash, On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> wrote: > > > -----Original Message----- > > From: Bin Meng <bmeng.cn@gmail.com> > > Sent: 10 December 2020 19:05 > > To: Yash Shah <yash.shah@openfive.com> > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > > C000 SoC > > > > [External Email] Do not click links or attachments unless you recognize the > > sender and know the content is safe > > > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> wrote: > > > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built > > > > FU740-C000 Soc > > > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > > > This file is expected to grow as more device drivers are added to the > > > kernel. > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > --- > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > > +++++++++++++++++++++++++++++ > > > 1 file changed, 293 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > new file mode 100644 > > > index 0000000..eeb4f8c3 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > @@ -0,0 +1,293 @@ > > ... > > > > + plic0: interrupt-controller@c000000 { > > > + #interrupt-cells = <1>; > > > + #address-cells = <0>; > > > + compatible = "sifive,fu540-c000-plic", > > > + "sifive,plic-1.0.0"; > > > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > > That's because it is not required. There won't be any difference in driver code for FU740 plic. Are there any driver changes for the drivers that have an updated fu640-c000-* bindings? I don't see them in the linux-riscv list. > > ... > > > > + eth0: ethernet@10090000 { > > > + compatible = "sifive,fu540-c000-gem"; > > > > "sifive,fu740-c000-gem"? > > > > Same reason as above. > > Thanks for your review. Regards, Bin
> -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 16 December 2020 11:36 > To: Yash Shah <yash.shah@openfive.com> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > C000 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > Hi Yash, > > On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> > wrote: > > > > > -----Original Message----- > > > From: Bin Meng <bmeng.cn@gmail.com> > > > Sent: 10 December 2020 19:05 > > > To: Yash Shah <yash.shah@openfive.com> > > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > > > kernel@vger.kernel.org>; linux-riscv > > > <linux-riscv@lists.infradead.org>; > > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM > > > <linux- gpio@vger.kernel.org>; broonie@kernel.org; Greg > > > Kroah-Hartman <gregkh@linuxfoundation.org>; Albert Ou > > > <aou@eecs.berkeley.edu>; lee.jones@linaro.org; > > > u.kleine-koenig@pengutronix.de; Thierry Reding > > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > > > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > Rob > > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > > > <bgolaszewski@baylibre.com>; Linus Walleij > > > <linus.walleij@linaro.org> > > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the > > > SiFive FU740- > > > C000 SoC > > > > > > [External Email] Do not click links or attachments unless you > > > recognize the sender and know the content is safe > > > > > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> > wrote: > > > > > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is > > > > built > > > > > > FU740-C000 Soc > > > > > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > > > > > This file is expected to grow as more device drivers are added to > > > > the kernel. > > > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > > --- > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > > > +++++++++++++++++++++++++++++ > > > > 1 file changed, 293 insertions(+) create mode 100644 > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > new file mode 100644 > > > > index 0000000..eeb4f8c3 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > @@ -0,0 +1,293 @@ > > > > ... > > > > > > + plic0: interrupt-controller@c000000 { > > > > + #interrupt-cells = <1>; > > > > + #address-cells = <0>; > > > > + compatible = "sifive,fu540-c000-plic", > > > > + "sifive,plic-1.0.0"; > > > > > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > > > > That's because it is not required. There won't be any difference in driver > code for FU740 plic. > > Are there any driver changes for the drivers that have an updated > fu640-c000-* bindings? I don't see them in the linux-riscv list. Yes, they will be posted soon. - Yash > > > > > ... > > > > > > + eth0: ethernet@10090000 { > > > > + compatible = "sifive,fu540-c000-gem"; > > > > > > "sifive,fu740-c000-gem"? > > > > > > > Same reason as above. > > > > Thanks for your review. > > Regards, > Bin
On Mon, 07 Dec 2020 20:55:32 PST (-0800), yash.shah@sifive.com wrote: > Start board support by adding initial support for the SiFive FU740 SoC > and the first development board that uses it, the SiFive HiFive > Unmatched A00. > > Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the > U-boot and OpenSBI. > > This patch series is dependent on Zong's Patchset[0]. The patchset also > adds two new nodes in dtsi file. The binding documentation patch > for these nodes are already posted on the mailing list[1][2]. > > [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u > [1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.shah@sifive.com/T/#t > [2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong.li@sifive.com/T/#u > > Changes in v2: > - The dt bindings patch is split into several individual patches. > - Expand the full list for compatible strings in i2c-ocores.txt > > Yash Shah (9): > dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC > dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC > dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC > dt-bindings: serial: Update DT binding docs to support SiFive FU740 > SoC > dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC > dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC > riscv: dts: add initial support for the SiFive FU740-C000 SoC > dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched > board > riscv: dts: add initial board data for the SiFive HiFive Unmatched > > .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +- > .../devicetree/bindings/i2c/i2c-ocores.txt | 8 +- > .../devicetree/bindings/pwm/pwm-sifive.yaml | 9 +- > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 + > .../devicetree/bindings/riscv/sifive.yaml | 17 +- > .../devicetree/bindings/serial/sifive-serial.yaml | 4 +- > .../devicetree/bindings/spi/spi-sifive.yaml | 10 +- > arch/riscv/boot/dts/sifive/Makefile | 3 +- > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++ > .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++++++++++++++++++ > 10 files changed, 590 insertions(+), 17 deletions(-) > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi > create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts Thanks, these are on for-next. There was one checkpatch warning about the missing ISSI device tree entry, but we already had that in the FU540 so I'm OK letting it slide. I'm also not really sure this is the right way to do this sort of thing: most of the patches here really aren't RISC-V things, they're SiFive SOC things. Some of these patches have been picked up by other trees, but I just took the rest. I'm not all that happy about taking DT bindings for things like GPIO or PWM bindings, but as they're pretty small I'm OK doing it in this instance. In the future it would really be better to split these up and land them via their respectitve trees, rather than trying to do all the SOC stuff over here. I know that can be a headache, but we have that SOC group for this purpose to try and keep things a bit more together -- I know it was a while ago and there really hasn't been much SOC activity on the RISC-V side of things so maybe it hasn't been that widley discussed, but that was really designed to solve these sorts of problems.
Start board support by adding initial support for the SiFive FU740 SoC and the first development board that uses it, the SiFive HiFive Unmatched A00. Boot-tested on Linux 5.10-rc4 on a HiFive Unmatched A00 board using the U-boot and OpenSBI. This patch series is dependent on Zong's Patchset[0]. The patchset also adds two new nodes in dtsi file. The binding documentation patch for these nodes are already posted on the mailing list[1][2]. [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u [1]: https://lore.kernel.org/linux-riscv/1606714984-16593-1-git-send-email-yash.shah@sifive.com/T/#t [2]: https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong.li@sifive.com/T/#u Changes in v2: - The dt bindings patch is split into several individual patches. - Expand the full list for compatible strings in i2c-ocores.txt Yash Shah (9): dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC dt-bindings: spi: Update DT binding docs to support SiFive FU740 SoC dt-bindings: pwm: Update DT binding docs to support SiFive FU740 SoC dt-bindings: serial: Update DT binding docs to support SiFive FU740 SoC dt-bindings: gpio: Update DT binding docs to support SiFive FU740 SoC dt-bindings: i2c: Update DT binding docs to support SiFive FU740 SoC riscv: dts: add initial support for the SiFive FU740-C000 SoC dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board riscv: dts: add initial board data for the SiFive HiFive Unmatched .../devicetree/bindings/gpio/sifive,gpio.yaml | 4 +- .../devicetree/bindings/i2c/i2c-ocores.txt | 8 +- .../devicetree/bindings/pwm/pwm-sifive.yaml | 9 +- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 + .../devicetree/bindings/riscv/sifive.yaml | 17 +- .../devicetree/bindings/serial/sifive-serial.yaml | 4 +- .../devicetree/bindings/spi/spi-sifive.yaml | 10 +- arch/riscv/boot/dts/sifive/Makefile | 3 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 +++++++++++++++++++++ .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 ++++++++++++++++++ 10 files changed, 590 insertions(+), 17 deletions(-) create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi create mode 100644 arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts