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[2/2] pinctrl: renesas: r8a779f0: Fix GPIO function on I2C-capable pins

Message ID c12c60ec1058140a37f03650043ab73f730f104f.1650610471.git.geert+renesas@glider.be
State Accepted
Commit 8bdd369dba7ff2f89cfd723ca3a26602aae4e498
Headers show
Series pinctrl: renesas: rcar-gen4: Fix GPIO function on I2C-capable pins | expand

Commit Message

Geert Uytterhoeven April 22, 2022, 7:29 a.m. UTC
Unlike on R-Car Gen3 SoCs, setting a bit to zero in a GPIO / Peripheral
Function Select Register (GPSRn) on R-Car S4-8 is not always sufficient
to configure a pin for GPIO.  For I2C-capable pins, the I2C function
must also be explicitly disabled in the corresponding Module Select
Register (MODSELn).

Add the missing FN_SEL_I2Ci_0 function enums to the pinmux_data[] array
by temporarily overriding the GP_2_j_FN function enum to expand to two
enums: the original GP_2_j_FN enum to configure the GPSR register bits,
and the missing FN_SEL_I2Ci_0 enum to configure the MODSEL register
bits.

Fixes: 030ac6d7eeff81e3 ("pinctrl: renesas: Initial R8A779F0 PFC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Geert Uytterhoeven May 3, 2022, 8:01 a.m. UTC | #1
On Fri, Apr 22, 2022 at 9:29 AM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> Unlike on R-Car Gen3 SoCs, setting a bit to zero in a GPIO / Peripheral
> Function Select Register (GPSRn) on R-Car S4-8 is not always sufficient
> to configure a pin for GPIO.  For I2C-capable pins, the I2C function
> must also be explicitly disabled in the corresponding Module Select
> Register (MODSELn).
>
> Add the missing FN_SEL_I2Ci_0 function enums to the pinmux_data[] array
> by temporarily overriding the GP_2_j_FN function enum to expand to two
> enums: the original GP_2_j_FN enum to configure the GPSR register bits,

GP_1_j_FN

> and the missing FN_SEL_I2Ci_0 enum to configure the MODSEL register
> bits.
>
> Fixes: 030ac6d7eeff81e3 ("pinctrl: renesas: Initial R8A779F0 PFC support")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

queuing in renesas-pinctrl-for-v5.19, with the above fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
diff mbox series

Patch

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 69f3abca1e22b2b5..23676e509bba4fba 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -254,7 +254,28 @@  enum {
 };
 
 static const u16 pinmux_data[] = {
+/* Using GP_1_[9-0] requires disabling I2C in MOD_SEL1 */
+#define GP_1_0_FN	GP_1_0_FN,	FN_SEL_I2C0_0
+#define GP_1_1_FN	GP_1_1_FN,	FN_SEL_I2C0_0
+#define GP_1_2_FN	GP_1_2_FN,	FN_SEL_I2C1_0
+#define GP_1_3_FN	GP_1_3_FN,	FN_SEL_I2C1_0
+#define GP_1_4_FN	GP_1_4_FN,	FN_SEL_I2C2_0
+#define GP_1_5_FN	GP_1_5_FN,	FN_SEL_I2C2_0
+#define GP_1_6_FN	GP_1_6_FN,	FN_SEL_I2C3_0
+#define GP_1_7_FN	GP_1_7_FN,	FN_SEL_I2C3_0
+#define GP_1_8_FN	GP_1_8_FN,	FN_SEL_I2C4_0
+#define GP_1_9_FN	GP_1_9_FN,	FN_SEL_I2C4_0
 	PINMUX_DATA_GP_ALL(),
+#undef GP_1_0_FN
+#undef GP_1_1_FN
+#undef GP_1_2_FN
+#undef GP_1_3_FN
+#undef GP_1_4_FN
+#undef GP_1_5_FN
+#undef GP_1_6_FN
+#undef GP_1_7_FN
+#undef GP_1_8_FN
+#undef GP_1_9_FN
 
 	PINMUX_SINGLE(SD_WP),
 	PINMUX_SINGLE(SD_CD),