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From: Lijuan Gao <quic_lijuang@quicinc.com>
Date: Thu, 12 Dec 2024 17:24:04 +0800
Subject: [PATCH 5/6] arm64: dts: qcom: correct gpio-ranges for QCS615
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| Series |
Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300
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expand
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diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index c0e4b376a1c6..4c3d8e39ce0b 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -938,7 +938,7 @@ tlmm: pinctrl@3100000 { "west", "south"; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-ranges = <&tlmm 0 0 123>; + gpio-ranges = <&tlmm 0 0 124>; gpio-controller; #gpio-cells = <2>; interrupt-controller;
The QCS615 TLMM pin controller has GPIOs 0-122, it also has UFS_RESET pin for primary UFS memory reset, so correct the gpio-ranges for the UFS driver can toggle it. Fixes: 8e266654a2fe ("arm64: dts: qcom: add QCS615 platform") Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)