From patchwork Thu Sep 19 16:06:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Chan X-Patchwork-Id: 829698 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 165E61AAE3A; Thu, 19 Sep 2024 16:17:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726762624; cv=none; b=sE1E3gb0zkD2HcKXGF9EMA1V+N5ayQ4KN0BMfBa0KJPmoGnspnOFz+FWf1vP6tLcQrb3Dg0cFTomozjlbZDM1qmmFE4lCC0DOZBgr03SH67OxjbYMxrrcpz3ZddcHkRd+jXkSc0ezM1E3wlc+IsjbCSW6c+eubvbbR5vs6I/q+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726762624; c=relaxed/simple; bh=LPVkO9tbSVkdHI9z7yV79C1isk5CjuqNLVmpdW0CHk0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hueh7j9PHnwzEMeamEE6gUjfU5ht1kntlAXWNoC2iC949Dea6Lfrxc7mvXtd7omCBtyrPr+S/z79JigjdJ64zAD8nZaGb9/7FcUjGXvhY3/heSVVEycNXmeivCYaCKn0xXORnf+D3nu4kbKxJTUqkkL9hy2Q6f50XBFPKQpR9YU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=K68jqhgz; arc=none smtp.client-ip=209.85.216.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="K68jqhgz" Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-2d8b679d7f2so907757a91.1; Thu, 19 Sep 2024 09:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1726762621; x=1727367421; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BbBY9aKxwBwO+dv7P65Zv7bGyM0waEH+w3/C1Oh6LY4=; b=K68jqhgzOkzPGEoqaYg+AAhxZHKrEXzIQD/UR2zq54oyrv0Old3csF1YpAAle868fw 6dk9y79hdp7XdCFI51lgf6lGSM+Bta0Y/offsJE++M7FxnuwhuA3wUe345xDjq1U3uRV a3HmK41evZ9oswAulVWXlif4BeSZFFagmsKuforAHYGgSHhv+Lr2zF2VpQhy55N/DN2F 9i/pMWyheHbMxd0EA9We1mES/txbPvMHCOfuNJlgrSDfN2559HCk7QXVbfQupEIV2M5H Hg1nRJQykiXUN4xxTfl5s/vAJJTG0KMyWUiBRxCDaltkZkd7WiokC8H7jz/QJqPSq/uY wmPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1726762621; x=1727367421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BbBY9aKxwBwO+dv7P65Zv7bGyM0waEH+w3/C1Oh6LY4=; b=riy5Aef5zreWxDxlmKysuuD1ORPaVpXQgap9iY4BMsRKukucPbStf1YPGnrheP84fo 85Xq/zk+wioYaPtrM7y6emwXGRMKf7wGwcdAMRhXGQ3qbn6l1icAHd5vHCQpgdpYOVtk XjOeHH2lwSRnDj6QwXdxWDg4kS7MNEoxSNzv8xdX7BqTb1ZBkCOYD+IkF1ewxgWqQG4N Kuaok+vwo4emx22VmhXsJJt3ssHUl/tJRYmi0wlFqqC2f2JJTd6mGZFwx+o7GaNTLtpa U4BrFexbJ8TnV95xwiKaIktWdbEBWOBzwdUy53rDhG4t3lpHpC81XLEsBZjltIi8x2Vg +fHw== X-Forwarded-Encrypted: i=1; AJvYcCUTG/LMIY+2osxmRdo+hE7/VwZd3jnXq5GHO0UB3ycjq6nLSdK2t1QJZsFlTLeAMQ46p8VoHryqrBiVvPlA4WU=@vger.kernel.org, AJvYcCUbRPDFchMuxk/w6P60vRo5buSxnQwxfUylMvdDz658kmvuj487UrX0OJp2NENuX5rQeLUCQ+IZAS7F@vger.kernel.org, AJvYcCWmgKKI+sQR7QpUN9OeQkxqfOISry8vJljR4bdwR9EEfFKKeGIRmRcd0LF6v063jJxcR6mNwmfYUxrLew==@vger.kernel.org, AJvYcCWuxyTO4YnOqnK//8rZUz35X9bwWvjmLNHRGCzc0t1GCPsTRTckbB3PoEHsw5IjszOwtltL8PPHq7tmT3HS@vger.kernel.org X-Gm-Message-State: AOJu0YwJgCnbWgVq16USg8HMl+1mQlKV15Fd5w9UnSmPXd6euFHqfXAH OlH/TbvwkZNRibaF4TJKhAncsQ8kJsvtY3EObc42+cOd1Kh01fc3 X-Google-Smtp-Source: AGHT+IFbT7VSjvrmVpDDqpCZnqT/QnI38jLYyKA4241/uXmGmajSsvOApxERqPdXkvz6+xRqohEM8A== X-Received: by 2002:a17:90a:c10:b0:2d8:8991:211f with SMTP id 98e67ed59e1d1-2dba0048376mr33339260a91.28.1726762621333; Thu, 19 Sep 2024 09:17:01 -0700 (PDT) Received: from localhost.localdomain ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2dd6eed1865sm2084674a91.34.2024.09.19.09.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2024 09:17:00 -0700 (PDT) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Wim Van Sebroeck , Guenter Roeck , Catalin Marinas , Will Deacon , Lorenzo Pieralisi , Mark Kettenis , asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Cc: konradybcio@kernel.org, ivo.ivanov.ivanov1@gmail.com, towinchenmi@gmail.com Subject: [PATCH v4 19/20] arm64: dts: apple: Add A11 devices Date: Fri, 20 Sep 2024 00:06:08 +0800 Message-ID: <20240919161443.10340-20-towinchenmi@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240919161443.10340-1-towinchenmi@gmail.com> References: <20240919161443.10340-1-towinchenmi@gmail.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Konrad Dybcio Add DTS files for the A11 SoC and the following devices based on it: - iPhone 8 - iPhone 8 Plus - iPhone X On A11, Apple has introduced independent performance and efficiency core clusters, so indicate it in the device tree as well. Signed-off-by: Konrad Dybcio [Nick: SMP and m1n1 support, disabled SMC pinctrl] Co-developed-by: Nick Chan Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/Makefile | 6 + arch/arm64/boot/dts/apple/t8015-8.dtsi | 16 ++ arch/arm64/boot/dts/apple/t8015-8plus.dtsi | 9 + arch/arm64/boot/dts/apple/t8015-d20.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d201.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d21.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d211.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d22.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-d221.dts | 14 ++ arch/arm64/boot/dts/apple/t8015-x.dtsi | 16 ++ arch/arm64/boot/dts/apple/t8015.dtsi | 268 +++++++++++++++++++++ 11 files changed, 399 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8015-8.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8015-8plus.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8015-d20.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d201.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d21.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d211.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d22.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-d221.dts create mode 100644 arch/arm64/boot/dts/apple/t8015-x.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8015.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index a44c14fae7bc..ab6ebb53218a 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -46,6 +46,12 @@ dtb-$(CONFIG_ARCH_APPLE) += t8011-j120.dtb dtb-$(CONFIG_ARCH_APPLE) += t8011-j121.dtb dtb-$(CONFIG_ARCH_APPLE) += t8011-j207.dtb dtb-$(CONFIG_ARCH_APPLE) += t8011-j208.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8015-d201.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8015-d20.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8015-d211.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8015-d21.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8015-d221.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8015-d22.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j274.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j293.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j313.dtb diff --git a/arch/arm64/boot/dts/apple/t8015-8.dtsi b/arch/arm64/boot/dts/apple/t8015-8.dtsi new file mode 100644 index 000000000000..cac1d47285a1 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-8.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include "t8015.dtsi" + +/ { + chassis-type = "handset"; +}; + +&serial0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-8plus.dtsi b/arch/arm64/boot/dts/apple/t8015-8plus.dtsi new file mode 100644 index 000000000000..ea291a95f028 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-8plus.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 Plus common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +/* The 8 Plus has minor differences like 1 more camera, 1 GiB of RAM more and a bigger display. */ +#include "t8015-8.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8015-d20.dts b/arch/arm64/boot/dts/apple/t8015-d20.dts new file mode 100644 index 000000000000..35d79e2ceebc --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d20.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 (Global), D20 iPhone10,1 (A1863/A1906/A1907) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-8.dtsi" + +/ { + compatible = "apple,d20", "apple,t8015", "apple,arm-platform"; + model = "Apple iPhone 8 (Global)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d201.dts b/arch/arm64/boot/dts/apple/t8015-d201.dts new file mode 100644 index 000000000000..31e0947fee70 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d201.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 (GSM), D20 iPhone10,4 (A1905) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-8.dtsi" + +/ { + compatible = "apple,d201", "apple,t8015", "apple,arm-platform"; + model = "Apple iPhone 8 (GSM)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d21.dts b/arch/arm64/boot/dts/apple/t8015-d21.dts new file mode 100644 index 000000000000..a902ba7f1133 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d21.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 Plus (Global), D21 iPhone10,2 (A1864/A1897/A1898) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-8plus.dtsi" + +/ { + compatible = "apple,d21", "apple,t8015", "apple,arm-platform"; + model = "Apple iPhone 8 Plus (Global)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d211.dts b/arch/arm64/boot/dts/apple/t8015-d211.dts new file mode 100644 index 000000000000..3b3f886c0c09 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d211.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone 8 Plus (GSM), D211 iPhone10,5 (A1899) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-8plus.dtsi" + +/ { + compatible = "apple,d211", "apple,t8015", "apple,arm-platform"; + model = "Apple iPhone 8 Plus (GSM)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d22.dts b/arch/arm64/boot/dts/apple/t8015-d22.dts new file mode 100644 index 000000000000..5a7a6092c2d0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d22.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone X (Global), D22, iPhone10,3 (A1865) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-x.dtsi" + +/ { + compatible = "apple,d22", "apple,t8015", "apple,arm-platform"; + model = "Apple iPhone X (Global)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-d221.dts b/arch/arm64/boot/dts/apple/t8015-d221.dts new file mode 100644 index 000000000000..dd920c945bd6 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-d221.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone X (GSM), D221, iPhone10,6 (A1901) + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include "t8015-x.dtsi" + +/ { + compatible = "apple,d221", "apple,t8015", "apple,arm-platform"; + model = "Apple iPhone X (GSM)"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015-x.dtsi b/arch/arm64/boot/dts/apple/t8015-x.dtsi new file mode 100644 index 000000000000..afba4944656b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015-x.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPhone X common device tree + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include "t8015.dtsi" + +/ { + chassis-type = "handset"; +}; + +&serial0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi new file mode 100644 index 000000000000..ceb245e270b3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8015 "A11" SoC + * + * Copyright (c) 2022, Konrad Dybcio + * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. + */ + +#include +#include +#include +#include + +/ { + interrupt-parent = <&aic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e0>; + }; + core1 { + cpu = <&cpu_e1>; + }; + core2 { + cpu = <&cpu_e2>; + }; + core3 { + cpu = <&cpu_e3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p0>; + }; + core1 { + cpu = <&cpu_p1>; + }; + }; + }; + + cpu_e0: cpu@0 { + compatible = "apple,mistral"; + reg = <0x0 0x0>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu_e1: cpu@1 { + compatible = "apple,mistral"; + reg = <0x0 0x1>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu_e2: cpu@2 { + compatible = "apple,mistral"; + reg = <0x0 0x2>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu_e3: cpu@3 { + compatible = "apple,mistral"; + reg = <0x0 0x3>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu_p0: cpu@10004 { + compatible = "apple,monsoon"; + reg = <0x0 0x10004>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu_p1: cpu@10005 { + compatible = "apple,monsoon"; + reg = <0x0 0x10005>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0 0>; /* To be filled by loader */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The bootloader reserves a region for the (varying-address, depending + * on what FW your device runs AND model) framebuffer under this node. + */ + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + nonposted-mmio; + ranges; + + serial0: serial@22e600000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x2e600000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + /* Use the bootloader-enabled clocks for now. */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + aic: interrupt-controller@232100000 { + compatible = "apple,t8015-aic", "apple,aic"; + reg = <0x2 0x32100000 0x0 0x8000>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + pinctrl_ap: pinctrl@233100000 { + compatible = "apple,t8015-pinctrl", "apple,pinctrl"; + reg = <0x2 0x33100000 0x0 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 223>; + apple,npins = <223>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@2340f0000 { + compatible = "apple,t8015-pinctrl", "apple,pinctrl"; + reg = <0x2 0x340f0000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 49>; + apple,npins = <49>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pinctrl_nub: pinctrl@2351f0000 { + compatible = "apple,t8015-pinctrl", "apple,pinctrl"; + reg = <0x2 0x351f0000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_nub 0 0 8>; + apple,npins = <8>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + ; + }; + + wdt: watchdog@2352b0000 { + compatible = "apple,t8015-wdt", "apple,wdt"; + reg = <0x2 0x352b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pinctrl_smc: pinctrl@236024000 { + compatible = "apple,t8015-pinctrl", "apple,pinctrl"; + reg = <0x2 0x36024000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 6>; + apple,npins = <6>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + /* + * SMC is not yet supported and accessing this pinctrl while SMC is + * suspended results in a hang. + */ + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt"; + /* Note that A11 doesn't actually have a hypervisor (EL2 is not implemented). */ + interrupts = , + ; + }; +};