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AJvYcCUBgAKFJuoxg9kPX/a7rHhXaRNYljvVAiJxOf/YZNKkGZbeHEd+TEG8IERhiJVxOA44PrFc4cpnizyB@vger.kernel.org, AJvYcCUixA3GOoiJU2X3m5/pSJCF8RDUNPLVdbnbcByNRX85/Z1PWWUIgOnmfzPwV6RqWRCrIpAMvYIrotxqYA==@vger.kernel.org, AJvYcCViZcP9uUFXrJ8RP01e12KpU0wKdH0BG+4nMx2SMusKZRmbgJOya0VkvQEFSpmDvP3r48ptIfKaOibxHgdY@vger.kernel.org X-Gm-Message-State: AOJu0YxVqTEoEFcSrYnq/4VpO6KufpR9VXfy/+44/4gJEdHDgcmn5GBq Jh2WViX+9pSHxopOTc0SngpnreyMU9vD8wC9pYCLrybFltIftclUcAMX3Q== X-Google-Smtp-Source: AGHT+IEq6/2e51ev4Ch2Nwkl3CyGCR2R6OIHKXExqBzzYnk8Ct2yDN0l9hZ/x7veEZM2i55zQJPC3w== X-Received: by 2002:a17:907:6e8f:b0:a8d:c3b:b16 with SMTP id a640c23a62f3a-a9047d1afaemr1613314066b.28.1726661381440; Wed, 18 Sep 2024 05:09:41 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:2595:4364:d152:dff3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a90612b384fsm584440366b.142.2024.09.18.05.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2024 05:09:40 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 3/3] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger Date: Wed, 18 Sep 2024 13:09:09 +0100 Message-Id: <20240918120909.284930-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240918120909.284930-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240918120909.284930-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add support for configuring the multiplexed pins as schmitt-trigger inputs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 42181cc877fe..60ef20ca3ccf 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -140,6 +140,7 @@ #define PUPD(off) (0x1C00 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) #define NOD(off) (0x3000 + (off) * 8) +#define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) @@ -162,6 +163,7 @@ #define SR_MASK 0x01 #define PUPD_MASK 0x03 #define NOD_MASK 0x01 +#define SMT_MASK 0x01 #define PM_INPUT 0x1 #define PM_OUTPUT 0x2 @@ -1348,6 +1350,15 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(cfg & PIN_CFG_SMT)) + return -EINVAL; + + arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); + if (!arg) + return -EINVAL; + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL; @@ -1484,6 +1495,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, 1); break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (!(cfg & PIN_CFG_SMT)) + return -EINVAL; + + rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); + break; + case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: if (!(cfg & PIN_CFG_IOLH_RZV2H)) return -EINVAL;