From patchwork Wed Sep 11 19:50:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 827528 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 224161BA277; Wed, 11 Sep 2024 19:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726084268; cv=none; b=BKqp1Cf6tv4kTx784rXhY5mzrMCDXjQJLtDj8jQrUi2Rrzni18DeJ+pPMqH9sBvFXPc6ZCLVMj2kl+f1M2W/UuV1KISXx5Fm06RJxsNNU+zoU4e6E7QwG93wtPGeqffhNgncYvFdfrhJdOVUQESJIEwJ6VOPInnp7O9kuHP97Ek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726084268; c=relaxed/simple; bh=dt62leiaZPP+WTW3BBP/jAts/x45Hc9lz8dh3jdicJc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uONydk9iY6bXFLAPAqQGGUC++FpOUlrcO8TmESYbEjAi8Lrg8Tl6+vMzCJ4gRfpMNPtMREgT0iUG/S73GzQVlIb+m+H5qdjxNrOfaSnrzkXlZGOVLOXCz+9C0XmYzQlMERmAIQuATL3K5F7UrA4Gceyum9RrPfX6w4tvGRRxDPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kU8yDb2V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kU8yDb2V" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 235AFC4CEC0; Wed, 11 Sep 2024 19:51:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726084267; bh=dt62leiaZPP+WTW3BBP/jAts/x45Hc9lz8dh3jdicJc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kU8yDb2V9lbvzLJ22LtdxtKp+MtXKeW5B+MaTlBF3MWzOFPA1CkIhsiSrdNVEAqmY /5xR6fBGPZ9dBqydPcXy7cyGHCV3qP2QAtuensNz5+NQrJ9v+fsKrBhtG+AZ9ITCZ5 4R2d0qOREko/UVVfL0w/KiQzy+xWA9PsI06fg9TRSma9ruXtIrQS8N/esQNnH3jc7P duLSVT6RbLSiNy4QxswgzrhzyQkrBNXPQLiUxawGw0SNLnC17O8YEFzAg0vw/Qlpsl H4XltZctly5FzFEZGI28/rPduDTU3GCn0hAMDcTDRNypGBgPTzf3g+xNyctSjnP9q5 fOISwHdnXyo1A== From: Lorenzo Bianconi Date: Wed, 11 Sep 2024 21:50:01 +0200 Subject: [PATCH v4 1/5] dt-bindings: arm: airoha: Add the chip-scu node for EN7581 SoC Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240911-en7581-pinctrl-v4-1-60ac93d760bb@kernel.org> References: <20240911-en7581-pinctrl-v4-0-60ac93d760bb@kernel.org> In-Reply-To: <20240911-en7581-pinctrl-v4-0-60ac93d760bb@kernel.org> To: Lorenzo Bianconi , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sean Wang , Matthias Brugger , AngeloGioacchino Del Regno , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Cc: linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, upstream@airoha.com, benjamin.larsson@genexis.eu, ansuelsmth@gmail.com, linux-pwm@vger.kernel.org X-Mailer: b4 0.14.1 This patch adds the chip-scu document bindings for EN7581 SoC. The airoha chip-scu block provides a configuration interface for clock, io-muxing and other functionalities used by multiple controllers (e.g. clock, pinctrl, ecc.) on EN7581 SoC. Reviewed-by: Rob Herring (Arm) Signed-off-by: Lorenzo Bianconi --- .../bindings/arm/airoha,en7581-chip-scu.yaml | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml new file mode 100644 index 000000000000..67c449d804c2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/airoha,en7581-chip-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Chip SCU Controller for EN7581 SoC + +maintainers: + - Lorenzo Bianconi + +description: + The airoha chip-scu block provides a configuration interface for clock, + io-muxing and other functionalities used by multiple controllers (e.g. clock, + pinctrl, ecc) on EN7581 SoC. + +properties: + compatible: + items: + - enum: + - airoha,en7581-chip-scu + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + syscon@1fa20000 { + compatible = "airoha,en7581-chip-scu", "syscon"; + reg = <0x0 0x1fa20000 0x0 0x388>; + }; + };