From patchwork Tue Jun 18 12:08:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= X-Patchwork-Id: 805443 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A558013C3CC; Tue, 18 Jun 2024 12:09:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718712556; cv=none; b=EJvYjp62OhPhrGyKpqMb5ixBqEQoBYeMP/EwZGhm10V/8c36kDw7aKjQ09JsfveS8SPx6mvEKSfrX++Cp14+hbRwwdPvY93xf0OBbF2mnAffefDuyeiF4icrJualJTLStOjSM1ywNVzdZc7UPNiWTdbw2wdAIj74+shiXN9jmIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718712556; c=relaxed/simple; bh=M20NbBpDh1F5HaGtzwdKev37C19nzMd1eSdVMlGPyaE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=n05DqYck4hNCT9URgJI0lwbetJNkdokUjkYpKPKP7poYQ5KJYnTX30Cqz4CVSaWXiIPyOdkRsMG4WvIlEkzwq06FYK94M7XMkJj0auqO0ynxSU0iSUnZ8f0eH1I1d1u0yCVsId2YsBITkgRh++dNpI0Qe6oLn4z9i+FDuxLXKo8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nQ9uErXI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nQ9uErXI" Received: by smtp.kernel.org (Postfix) with ESMTPS id 707B0C4DDEC; Tue, 18 Jun 2024 12:09:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718712556; bh=M20NbBpDh1F5HaGtzwdKev37C19nzMd1eSdVMlGPyaE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nQ9uErXISc5pfsqdodAvlW/qR65n72C6gRv9xuEbMQYnyJYdJlDCEGopyrN39RcrN FDWhh8+uytHGGhr08X7swFurDFiKRKC1Qde1tQjTTBONFtOQIXG8VZRz1sZhTQoUie 4ob/66mmDaIOWleLaYOzTlQYHoPrZsYiWPxTFY/ckyB6OF92zuqIbshZBwVwSmESFm Z5Fs9Eb2hicFKgRV+sJjPpVvFSJlg7M/TL2gBEGkbIOpUr7u6vpWxX9jZElR9842eb quADXzSFWGyDY9zhOZrdoCGOfu4Vdy9l3JZQobd8tlMFhIvb3e8I546EGG/JpUh6HT AFHNj3fhutSKA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67E1AC2BB85; Tue, 18 Jun 2024 12:09:16 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 18 Jun 2024 14:08:18 +0200 Subject: [PATCH RESEND v10 07/12] clk: mmp: Add Marvell PXA1908 APMU driver Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240618-pxa1908-lkml-v10-7-754e5ece9078@skole.hr> References: <20240618-pxa1908-lkml-v10-0-754e5ece9078@skole.hr> In-Reply-To: <20240618-pxa1908-lkml-v10-0-754e5ece9078@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Tony Luck , "Guilherme G. Piccoli" , Rob Herring , Kees Cook Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5652; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=Etv7/TUpy5hEHvEFF1V/rXkT1DDO+Xoj32i8URRY6N4=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBmcXjScd7RAUsrPePOxprV3WWnIysg9hcz9e73e e5zfmnLKKuJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZnF40gAKCRCaEZ6wQi2W 4RsGD/9njZQvRaNFS4cDqNRg++fydF2C4TCWPt6Ey6L5IuijyOsvDiuNOsCsurbczPWap+F462i /6odhUHHoidi4WExhX/Nbj9wcS9DoqTprUgV4qVz7aefLeq+fxb5++eCWKl+VKd26BYALXkidFw BeCgQ0YsaXTfX1ZX/e/dx+4u6L30FATendWmna8WPWFRWz6Y4ErFXOs/flXBCOi4OSU+asAhCYx fxSEBsrlCvhQIjaSBWpOgH51QCWm/2FwjOl15jhSvfpRqD2hshM8MJZIF6Ix4RXOSn2io8Q0DpM xfUjRQtM7VXxxozwktXiras3QaJowKs2MIzKujKvSkjrPPaVNp6ZMWtbHxJMChxGBVKSv4xUjAd 0ucoy1GBedK78ybsyRvAg4eaYV7ev/D9JRqBfXX1RuBlO9MZgTjsNCSDps5g1tCXAZnhwLnOXgG r/hMnplzLi4HY39/taU4OlCzFA/vkh974zsBEHdiF/o4YQq8rBHFNCq0HLKHjWWHlCRm7pR2siy WFzXaxBYnSvG9OhQLM++k4g26x4eio3YUKBT9dM4BehPAEqOhqjq48bK6EE4tE5fk23gvlkB7VR A4ROY6WR8+d+/nFFl2TLKNcaxPJPMtmeRl9fuEhNsSTUgjS4mE572eRSLxUOdFhQilOMZG0sS5B FUQykymrq4lw91w== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/default with auth_id=112 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanović Add driver for the APMU controller block found on Marvell's PXA1908 SoC. This driver is incomplete, lacking support for (at least) GPU, VPU, DSI and CCIC (camera related) clocks. Signed-off-by: Duje Mihanović --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-pxa1908-apmu.c | 123 +++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index 038bcd4d035e..a8b1a4b08824 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o -obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o +obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o clk-pxa1908-apmu.o diff --git a/drivers/clk/mmp/clk-pxa1908-apmu.c b/drivers/clk/mmp/clk-pxa1908-apmu.c new file mode 100644 index 000000000000..693254539063 --- /dev/null +++ b/drivers/clk/mmp/clk-pxa1908-apmu.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define APMU_CLK_GATE_CTRL 0x40 +#define APMU_CCIC1 0x24 +#define APMU_ISP 0x38 +#define APMU_DSI1 0x44 +#define APMU_DISP1 0x4c +#define APMU_CCIC0 0x50 +#define APMU_SDH0 0x54 +#define APMU_SDH1 0x58 +#define APMU_USB 0x5c +#define APMU_NF 0x60 +#define APMU_VPU 0xa4 +#define APMU_GC 0xcc +#define APMU_SDH2 0xe0 +#define APMU_GC2D 0xf4 +#define APMU_TRACE 0x108 +#define APMU_DVC_DFC_DEBUG 0x140 + +#define APMU_NR_CLKS 17 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *base; +}; + +static DEFINE_SPINLOCK(pll1_lock); +static struct mmp_param_general_gate_clk pll1_gate_clks[] = { + {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock}, + {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lock}, +}; + +static DEFINE_SPINLOCK(sdh0_lock); +static DEFINE_SPINLOCK(sdh1_lock); +static DEFINE_SPINLOCK(sdh2_lock); + +static const char * const sdh_parent_names[] = {"pll1_416", "pll1_624"}; + +static struct mmp_clk_mix_config sdh_mix_config = { + .reg_info = DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11), +}; + +static struct mmp_param_gate_clk apmu_gate_clks[] = { + {PXA1908_CLK_USB, "usb_clk", NULL, 0, APMU_USB, 0x9, 0x9, 0x1, 0, NULL}, + {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH0, 0x12, 0x12, 0x0, 0, &sdh0_lock}, + {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH1, 0x12, 0x12, 0x0, 0, &sdh1_lock}, + {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, APMU_SDH2, 0x12, 0x12, 0x0, 0, &sdh2_lock} +}; + +static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit = &pxa_unit->unit; + + mmp_register_general_gate_clks(unit, pll1_gate_clks, + pxa_unit->base, ARRAY_SIZE(pll1_gate_clks)); + + sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH0; + mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh0_lock); + sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH1; + mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh1_lock); + sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->base + APMU_SDH2; + mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names, + ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, + &sdh_mix_config, &sdh2_lock); + + mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->base, + ARRAY_SIZE(apmu_gate_clks)); +} + +static int pxa1908_apmu_probe(struct platform_device *pdev) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); + if (IS_ERR(pxa_unit)) + return PTR_ERR(pxa_unit); + + pxa_unit->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pxa_unit->base)) + return PTR_ERR(pxa_unit->base); + + mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, APMU_NR_CLKS); + + pxa1908_axi_periph_clk_init(pxa_unit); + + return 0; +} + +static const struct of_device_id pxa1908_apmu_match_table[] = { + { .compatible = "marvell,pxa1908-apmu" }, + { } +}; +MODULE_DEVICE_TABLE(of, pxa1908_apmu_match_table); + +static struct platform_driver pxa1908_apmu_driver = { + .probe = pxa1908_apmu_probe, + .driver = { + .name = "pxa1908-apmu", + .of_match_table = pxa1908_apmu_match_table + } +}; +module_platform_driver(pxa1908_apmu_driver); + +MODULE_AUTHOR("Duje Mihanović "); +MODULE_DESCRIPTION("Marvell PXA1908 APMU Clock Driver"); +MODULE_LICENSE("GPL");