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AJvYcCVQ05Rc8qnI+7rIsMKER05zwTKc0cAw6S5w8DacwVNEhs+EIi5GHrmwsonJnmpzvrusVLykCPHlUbLMFl5iP2H3a0wQ5TdM7o4JbPAxkZSNOrwsHH5PhjoGwkRAqa4hmuac5XJiftxtsTIeDZxv/sAL9Zbxmbd5R+ERqx4g/FOXljR08CI= X-Gm-Message-State: AOJu0YwTNxK1/n7P67bUZUjiIEVZZdEFfiIh+I7X1oXyvtqqeE5fUooE lLkAXEqczqwcNywiAPq/Vyt0rlvXMMDhd3jQ6nVsz8I4IEIxihwU X-Google-Smtp-Source: AGHT+IGXSCyoFfAW1lwdv04gyPkv0INTSF/iy4XiFcyte8XtFbghK3TSuFG3iUHYLLffXAwnLyDcLQ== X-Received: by 2002:ac2:53a5:0:b0:51f:463c:c577 with SMTP id 2adb3069b0e04-5296410a5b4mr9026686e87.4.1716993879835; Wed, 29 May 2024 07:44:39 -0700 (PDT) Received: from yoga-710.tas.nnz-ipc.net ([178.218.200.115]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-529ac903bd9sm928915e87.236.2024.05.29.07.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 07:44:39 -0700 (PDT) From: Dmitry Yashin To: Linus Walleij , Heiko Stuebner Cc: Luca Ceresoli , Jianqun Xu , Jonas Karlman , devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin Subject: [PATCH v2 1/2] pinctrl: rockchip: delay recalced_mask and route_mask init Date: Wed, 29 May 2024 19:35:33 +0500 Message-ID: <20240529143534.32402-2-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240529143534.32402-1-dmt.yashin@gmail.com> References: <20240529143534.32402-1-dmt.yashin@gmail.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 For some SoC's like rk3308 additional runtime setup needed, so delay recalced_mask and route_mask init. Signed-off-by: Dmitry Yashin --- drivers/pinctrl/pinctrl-rockchip.c | 52 ++++++++++++++++++------------ 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index cc647db76927..c290c755b4fb 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3170,6 +3170,36 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, return 0; } +static void iomux_recalced_routes_init(struct rockchip_pinctrl *info) +{ + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_pin_bank *bank = ctrl->pin_banks; + int i, j; + + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { + + /* calculate the per-bank recalced_mask */ + for (j = 0; j < ctrl->niomux_recalced; j++) { + int pin = 0; + + if (ctrl->iomux_recalced[j].num == bank->bank_num) { + pin = ctrl->iomux_recalced[j].pin; + bank->recalced_mask |= BIT(pin); + } + } + + /* calculate the per-bank route_mask */ + for (j = 0; j < ctrl->niomux_routes; j++) { + int pin = 0; + + if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { + pin = ctrl->iomux_routes[j].pin; + bank->route_mask |= BIT(pin); + } + } + } +} + static const struct of_device_id rockchip_pinctrl_dt_match[]; /* retrieve the soc specific data */ @@ -3265,26 +3295,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( bank_pins += 8; } - - /* calculate the per-bank recalced_mask */ - for (j = 0; j < ctrl->niomux_recalced; j++) { - int pin = 0; - - if (ctrl->iomux_recalced[j].num == bank->bank_num) { - pin = ctrl->iomux_recalced[j].pin; - bank->recalced_mask |= BIT(pin); - } - } - - /* calculate the per-bank route_mask */ - for (j = 0; j < ctrl->niomux_routes; j++) { - int pin = 0; - - if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { - pin = ctrl->iomux_routes[j].pin; - bank->route_mask |= BIT(pin); - } - } } return ctrl; @@ -3403,6 +3413,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(info->regmap_pmu); } + iomux_recalced_routes_init(info); + ret = rockchip_pinctrl_register(pdev, info); if (ret) return ret;