From patchwork Thu Jan 4 02:42:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenhua Lin X-Patchwork-Id: 760062 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F880185B for ; Thu, 4 Jan 2024 02:43:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 4042hAVP001950; Thu, 4 Jan 2024 10:43:10 +0800 (+08) (envelope-from Wenhua.Lin@unisoc.com) Received: from SHDLP.spreadtrum.com (shmbx06.spreadtrum.com [10.0.1.11]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4T59hB2vDtz2Qby5B; Thu, 4 Jan 2024 10:36:26 +0800 (CST) Received: from xm9614pcu.spreadtrum.com (10.13.2.29) by shmbx06.spreadtrum.com (10.0.1.11) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Thu, 4 Jan 2024 10:43:08 +0800 From: Wenhua Lin To: Linus Walleij , Andy Shevchenko , Bartosz Golaszewski CC: Orson Zhai , Baolin Wang , Chunyan Zhang , , , wenhua lin , Wenhua Lin , Xiongpeng Wu Subject: [PATCH V3 4/4] gpio: eic-sprd: Support 8 banks EIC controller Date: Thu, 4 Jan 2024 10:42:44 +0800 Message-ID: <20240104024244.12163-5-Wenhua.Lin@unisoc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240104024244.12163-1-Wenhua.Lin@unisoc.com> References: <20240104024244.12163-1-Wenhua.Lin@unisoc.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To shmbx06.spreadtrum.com (10.0.1.11) X-MAIL: SHSQR01.spreadtrum.com 4042hAVP001950 In order to solve the problem of insufficient eic, it supports 8 banks of eic controller, each bank contains 8 eic. Signed-off-by: Wenhua Lin --- drivers/gpio/gpio-eic-sprd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c index 1ca3c444957c..715c7d581d7f 100644 --- a/drivers/gpio/gpio-eic-sprd.c +++ b/drivers/gpio/gpio-eic-sprd.c @@ -52,10 +52,10 @@ #define SPRD_EIC_SYNC_DATA 0x1c /* - * The digital-chip EIC controller can support maximum 3 banks, and each bank + * The digital-chip EIC controller can support maximum 8 banks, and each bank * contains 8 EICs. */ -#define SPRD_EIC_MAX_BANK 3 +#define SPRD_EIC_MAX_BANK 8 #define SPRD_EIC_PER_BANK_NR 8 #define SPRD_EIC_DATA_MASK GENMASK(7, 0) #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1)) @@ -627,9 +627,9 @@ static int sprd_eic_probe(struct platform_device *pdev) for (i = 0; i < SPRD_EIC_MAX_BANK; i++) { /* - * We can have maximum 3 banks EICs, and each EIC has + * We can have maximum 8 banks EICs, and each EIC has * its own base address. But some platform maybe only - * have one bank EIC, thus base[1] and base[2] can be + * have one bank EIC, thus base[1] to base[7] can be * optional. */ res = platform_get_resource(pdev, IORESOURCE_MEM, i);