From patchwork Thu Dec 7 07:06:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 751462 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="rT/be6Pj" Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CE17D5C for ; Wed, 6 Dec 2023 23:08:06 -0800 (PST) Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-54c74b3cd4cso1290865a12.1 for ; Wed, 06 Dec 2023 23:08:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1701932885; x=1702537685; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PWXKHpy1c4gjJzr0PzkBK/pN3/t8zDF0LUDKvRtnzbs=; b=rT/be6PjKAKs+pV0OXXzcHLs47lyAD0N01MEuG/iDqfxzq43xISfQ7R9zY9Yxnjvum PU0USvHkjGQL2HKbCXh3p5I8YVtIQNHlwcr4pQiDVXcpxzRNLtfDQr8WA5vOaUjO8JR8 tCc9SpNSpunukp+090F9UoZu0OsgNep0Dg6A0FiFtGUTSpMZvOoK5KAX715TJcxSFRBI Ef5OCMTLhqV+beDg78tDl6Ad4FqpP2AYJ+mSEHjiNaTFVwfMKgqFxxNB/OsSqgXRUJLy nQl03vWYT6GehPcEkb0R6Q5CcxSXkB+nAGZnb7yfFMDNuG3iD/AaKMGXOiF370+CsKW4 rTBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701932885; x=1702537685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PWXKHpy1c4gjJzr0PzkBK/pN3/t8zDF0LUDKvRtnzbs=; b=I2NBvIcv1gDg8MO9oT+vUE/I8AaYEQSb6pnG/AxqJxapRRSG5PbK+5SCh4WnvpItXJ 19AUgSHM5Wimf9evG7z8tTGtY0iXGMO8kaoBQV2N2rixKPE9AyDRJnqKRt5meMyA85IX 3ww/ydM2cT0Q6zfsNjhoFwaMEz6Gd7DV7WpevFn1JrdvamhRBLX/MEbsOZIEVlt7o3MH r4ehfnKsiAGOQAKt8SKESV32ZkmAME0ROWFBf7vAFTwfhLvyCXX4IxextuKrYuvjzMgB K4HII9JtVmdvN9xXz+IqZY1pPkvk2PrZvJS63AqNgl0fyuOV4rKIsA/6fO3cl58/XP1v gCmQ== X-Gm-Message-State: AOJu0YwEQxvy1t/q7nGfkUiVw3/sdirXzx+rBvpKUaO/eoT+YsV07NVc LD4Th3sT8Ej5nOWwTACPPY7FbA== X-Google-Smtp-Source: AGHT+IETRJWidR+eZ6Amb/oUqqk3EAj6S1ifekK+yyXNDYte9c3Us0ASM4lMk2pU+I8G94xgufnSsw== X-Received: by 2002:a50:a6d5:0:b0:54c:ada2:7fa1 with SMTP id f21-20020a50a6d5000000b0054cada27fa1mr2848300edc.16.1701932885084; Wed, 06 Dec 2023 23:08:05 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.22]) by smtp.gmail.com with ESMTPSA id b41-20020a509f2c000000b0054cb88a353dsm420818edf.14.2023.12.06.23.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 23:08:04 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 02/11] clk: renesas: r9a08g045-cpg: Add clock and reset support for ETH0 and ETH1 Date: Thu, 7 Dec 2023 09:06:51 +0200 Message-Id: <20231207070700.4156557-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea RZ/G3S has 2 Gigabit Ethernet interfaces available. Add clock and reset support for both of them. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - dropped MSTOP drivers/clk/renesas/r9a08g045-cpg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 4394cb241d99..a6d3bea968c0 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -181,9 +181,11 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS, dtable_1_32, 0, 0, 0, NULL), DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2), + DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1), DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2), DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1), DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3), + DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2), }; static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { @@ -202,6 +204,12 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), + DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0), + DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0), + DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8), + DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1), + DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1), + DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), }; @@ -212,6 +220,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), + DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0), + DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),