From patchwork Tue Oct 17 10:46:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 734794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 240D3C46CA1 for ; Tue, 17 Oct 2023 10:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343717AbjJQKr5 (ORCPT ); Tue, 17 Oct 2023 06:47:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234877AbjJQKr4 (ORCPT ); Tue, 17 Oct 2023 06:47:56 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD296EA; Tue, 17 Oct 2023 03:47:53 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40572aeb73cso54978935e9.3; Tue, 17 Oct 2023 03:47:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697539672; x=1698144472; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q8t4pyXTQWggodz/2IR/GDWp03fKEQSYUxVVcM38ngk=; b=EejYZyG5KdWSjVn07qiBRJfxX3fk7Kk6IF8yIFA72lqVoOHlWI+DRMdEgjhwl+tj3l WquO/N7Pm8pdAcvWdVks0jN21WtPRaY7MmCJSZgyMFYxWsJFU2h2/4+jL0jGsKsdQnQh vtYrGj/Z1ygsLW6icAEdkhQ94xH1pBGyaE8FZTgpNG4Fggwo3oz38VcNHDRYz/tJ19y3 gH1MTKEO6nD8CZjP5KRungHAJi4O1SIAIsxNhlnRoPvqxrqcbyPieYNQJr0ah8oWKsZv 3Cf7VF9hCU4kHJwcRbQHPCXMR7skAQ4RKMrd5tW4bheidtEwiuEljjd+Q4TM0vK1f5J3 2y6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697539672; x=1698144472; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q8t4pyXTQWggodz/2IR/GDWp03fKEQSYUxVVcM38ngk=; b=Hw0TFce4NSKTTQHeDo8dZDLLSnhpnaW0PPGAa55QVdPP03YNrE7aLPdg5OTGVY8b0x R6dV6iKT/GATaEgy5D1bffpdFWOS7iQZWUIHC2a5SP8/Wn38reRIOLQn7y26p/DP8Bx4 /DYhFR/VPUkJNIFMHLZisqvVxQWv3SA6A+vmlW0PZwCwcpHx6RsPiOuup3zrS53L6w6q SQodA9fm7fXwBpuJb4CB6P7vxIG0VD4EUM1UlV8aVoNzLVfFjpd7nsMkEg06lGLI/4nO Be3su9YvM0u5T8wlFm9rh8VClo36eHDMhEvulWrnGdZYX+hfvinWJZeKg1Pu/iAwRzR3 JhJw== X-Gm-Message-State: AOJu0YxWuZSRl9X5XCLlN+QAvvMluSI0czYvgo7+6bVKmz9ppXy2E+5m DMIpgix3Bds1un9rSRGWFlQ= X-Google-Smtp-Source: AGHT+IEZZ+8pNWDLWoOtxXpEw8Y2qeXYX7evHfDZFMZYvqirK7IEUxmL7eGpg/+vbjALQ5zMKBR/dA== X-Received: by 2002:a05:600c:41d6:b0:406:177e:5de8 with SMTP id t22-20020a05600c41d600b00406177e5de8mr1655071wmh.35.1697539672021; Tue, 17 Oct 2023 03:47:52 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:e26d:77db:3f90:862b]) by smtp.gmail.com with ESMTPSA id a6-20020a05600c348600b0040652e8ca13sm9582037wmq.43.2023.10.17.03.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 03:47:51 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Claudiu Beznea , Prabhakar , Lad Prabhakar Subject: [PATCH v2 2/3] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Date: Tue, 17 Oct 2023 11:46:37 +0100 Message-Id: <20231017104638.201260-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231017104638.201260-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20231017104638.201260-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Lad Prabhakar Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and is not identical for the complete port so introduced struct rzg2l_variable_pin_cfg to handle such cases and introduced PIN_CFG_VARIABLE macro. The actual pin config is then assigned rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 215 +++++++++++++++++++++++- 1 file changed, 213 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b0aeeb5ef3fa..b3c66eb1835a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -57,6 +57,8 @@ #define PIN_CFG_FILCLKSEL BIT(12) #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) +#define PIN_CFG_VARIABLE BIT(15) +#define PIN_CFG_NOGPIO_INT BIT(16) #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -82,6 +84,11 @@ */ #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) > 0 ? ((u64)(GENMASK_ULL(((n) - 1 + 28), 28))) : 0) | \ ((a) << 20) | (f)) +/* + * m indicates the bitmap of supported pins, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (((u64)(m) << 28) | ((a) << 20) | (f)) #define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK_ULL(35, 28)) >> 28) #define RZG2L_GPIO_PORT_GET_PINCNT(x) (hweight8(RZG2L_GPIO_PORT_GET_PINMAP((x)))) @@ -185,6 +192,18 @@ struct rzg2l_dedicated_configs { u64 config; }; +/** + * struct rzg2l_variable_pin_cfg - pin data cfg + * @cfg: port pin configuration + * @port: port number + * @pin: port pin + */ +struct rzg2l_variable_pin_cfg { + u32 cfg; + u8 port; + u8 pin; +}; + struct rzg2l_pinctrl_data { const char * const *port_pins; const u64 *port_pin_configs; @@ -193,6 +212,8 @@ struct rzg2l_pinctrl_data { unsigned int n_port_pins; unsigned int n_dedicated_pins; const struct rzg2l_hwcfg *hwcfg; + const struct rzg2l_variable_pin_cfg *variable_pin_cfg; + unsigned int n_variable_pin_cfg; }; /** @@ -228,6 +249,158 @@ struct rzg2l_pinctrl { static const u16 available_ps[] = { 1800, 2500, 3300 }; +#ifdef CONFIG_RISCV +static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, + u64 pincfg, + unsigned int port, + u8 pin) +{ + unsigned int i; + u8 pincount; + u8 pinmap; + u32 off; + + if (!pctrl->data->n_variable_pin_cfg) + return pincfg; + + for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { + if (pctrl->data->variable_pin_cfg[i].port == port && + pctrl->data->variable_pin_cfg[i].pin == pin) + break; + } + if (i == pctrl->data->n_variable_pin_cfg) + return pincfg; + + pinmap = RZG2L_GPIO_PORT_GET_PINMAP(pincfg); + pincount = RZG2L_GPIO_PORT_GET_PINCNT(pincfg); + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(pincfg); + + if (pinmap == pincount) + return RZG2L_GPIO_PORT_PACK(pincount, off, pctrl->data->variable_pin_cfg[i].cfg); + + return RZG2L_GPIO_PORT_SPARSE_PACK(pinmap, off, pctrl->data->variable_pin_cfg[i].cfg); +} + +static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { + { + .port = 20, + .pin = 0, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 6, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 7, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT + }, + { + .port = 23, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 0, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT, + }, +}; +#endif + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -1320,6 +1493,27 @@ static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), +#ifdef CONFIG_RISCV + /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ + RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ + RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */ + RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF | + PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT), /* P25 */ + 0x0, /* Dummy port P26 */ + 0x0, /* Dummy port P27 */ + RZG2L_GPIO_PORT_PACK(6, 0x0f, PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT), /* P28 */ +#endif }; static const u64 r9a08g045_gpio_configs[] = { @@ -1478,12 +1672,18 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { PIN_CFG_IO_VMC_SD1)) }, }; -static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) +static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; + const struct rzg2l_pinctrl_data *data = pctrl->data; + u64 *pin_data = pin_desc->drv_data; unsigned int gpioint; unsigned int i; u32 port, bit; + if (*pin_data & PIN_CFG_NOGPIO_INT) + return -EINVAL; + port = virq / 8; bit = virq % 8; @@ -1593,7 +1793,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned long flags; int gpioint, irq; - gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); + gpioint = rzg2l_gpio_get_gpioint(child, pctrl); if (gpioint < 0) return gpioint; @@ -1778,6 +1978,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) if (i && !(i % RZG2L_PINS_PER_PORT)) j++; pin_data[i] = pctrl->data->port_pin_configs[j]; +#ifdef CONFIG_RISCV + if (pin_data[i] & PIN_CFG_VARIABLE) + pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, + pin_data[i], + j, + i % RZG2L_PINS_PER_PORT); +#endif pins[i].drv_data = &pin_data[i]; } @@ -1925,6 +2132,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), .hwcfg = &rzg2l_hwcfg, +#ifdef CONFIG_RISCV + .variable_pin_cfg = r9a07g043f_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), +#endif }; static struct rzg2l_pinctrl_data r9a07g044_data = {