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Wed, 16 Aug 2023 06:58:47 -0700 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 16 Aug 2023 06:58:46 -0700 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Wed, 16 Aug 2023 06:58:45 -0700 From: Asmaa Mnebhi To: , , , , , CC: Asmaa Mnebhi Subject: [PATCH v1 2/2] gpio: mlxbf3: Support add_pin_ranges() Date: Wed, 16 Aug 2023 09:58:39 -0400 Message-ID: <20230816135839.24011-3-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20230816135839.24011-1-asmaa@nvidia.com> References: <20230816135839.24011-1-asmaa@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|PH7PR12MB6465:EE_ X-MS-Office365-Filtering-Correlation-Id: 5146b2b5-ff3d-4486-2f4f-08db9e60ef5e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 13:58:57.1783 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5146b2b5-ff3d-4486-2f4f-08db9e60ef5e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6465 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Support add_pin_ranges() so that pinctrl_gpio_request() can be called. The GPIO value is not modified when the user runs the "gpioset" tool. This is because when gpiochip_generic_request is invoked by the gpio-mlxbf3 driver, "pin_ranges" is empty so it skips "pinctrl_gpio_request()". pinctrl_gpio_request() is essential in the code flow because it changes the mux value so that software has control over modifying the GPIO value. Adding add_pin_ranges() creates a dependency on the pinctrl-mlxbf3.c driver. Fixes: cd33f216d24 ("gpio: mlxbf3: Add gpio driver support") Signed-off-by: Asmaa Mnebhi --- drivers/gpio/gpio-mlxbf3.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c index e30cee108986..3828f5282b17 100644 --- a/drivers/gpio/gpio-mlxbf3.c +++ b/drivers/gpio/gpio-mlxbf3.c @@ -158,6 +158,24 @@ static const struct irq_chip gpio_mlxbf3_irqchip = { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; +static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + int ret; + int id = 0; + + id = !!(chip->ngpio % MLXBF3_GPIO_MAX_PINS_PER_BLOCK); + + ret = gpiochip_add_pin_range(chip, + "MLNXBF34:00", + chip->base, + id * MLXBF3_GPIO_MAX_PINS_PER_BLOCK, + chip->ngpio); + if (ret) + return ret; + + return 0; +} + static int mlxbf3_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -197,6 +215,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev) gc->request = gpiochip_generic_request; gc->free = gpiochip_generic_free; gc->owner = THIS_MODULE; + gc->add_pin_ranges = mlxbf3_gpio_add_pin_ranges; irq = platform_get_irq(pdev, 0); if (irq >= 0) { @@ -243,6 +262,7 @@ static struct platform_driver mlxbf3_gpio_driver = { }; module_platform_driver(mlxbf3_gpio_driver); +MODULE_SOFTDEP("pre: pinctrl-mlxbf3"); MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver"); MODULE_AUTHOR("Asmaa Mnebhi "); MODULE_LICENSE("Dual BSD/GPL");