From patchwork Tue Apr 4 09:43:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 670635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B44C77B62 for ; Tue, 4 Apr 2023 09:43:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234338AbjDDJng (ORCPT ); Tue, 4 Apr 2023 05:43:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234106AbjDDJnd (ORCPT ); Tue, 4 Apr 2023 05:43:33 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC2012D42 for ; Tue, 4 Apr 2023 02:43:18 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id y20so41657439lfj.2 for ; Tue, 04 Apr 2023 02:43:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680601397; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MNYdQtD12ErxW9Tb9ALuTo8L9TpmlxX4Klxpk5H7jnk=; b=jYDIjklTKr8Cj1T9VYHcmDrIMw8h/xDvQ8AMsEyXG+GrHhNO6IT9GJzRVnpgvE4yOr bQ0iZBI8TaAJOXFbpWzOtgJL6eO+DTNoYJoUFm1SpNwJRbx4KIdU7BzH5hvCEIQROCfV UO7TGmAGOtDwu2qtnobq3CJ12F7/QAEvf9COV1OTAtdZvsQ9njcN3WU1ziJ2Tlk6Hbyv DdSrZZcOGKQvQVaF/j5ZLtSOL01ixH6Jb0wKyxDe9LegyLQ/2P6VG5YtKct2uf4iAp3B 6y8YnqYVJX/tsuFKs/z1r9qs7y/ylL6o40MaYO4Cg+S0mBerit+PSnXLxbzR2a9eNyVi l1GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680601397; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MNYdQtD12ErxW9Tb9ALuTo8L9TpmlxX4Klxpk5H7jnk=; b=FUMbu99904GRx/+sNzygj5a21IbZr07l+2EUfA4sPnEKiVOmPzsJuOnoEqCCB/06P9 v3AXRbbq1FVnCw78GSuQp+29FXTO/PUo8a/FWNL5g2nydX6Kkmh4jzFpa81niXGnH4MT U68CFiDH8Dqp3kE+tOioJ3FRa5Iq3de05cFZSTavSCZRQLBAXH9zWbEvfKXar+5xsJYl 0WBijRQJ7R0giOr3JSI0vfb0Gye6Bu4/K7aqoJPkhOzIjjMXmMIZ24oRVb8SxMsNBPNM CyRBkK6GQ0ioXA9znaQ7ryec3kOJwLTciwqNmg5M+DUCTqPomd20PnkpCbAcugRGuPYk 9Lsg== X-Gm-Message-State: AAQBX9def+dyEIIpquaFhtKxfXlAlHu1nk9aTKywOJsFmr+M5U8tmZUu XkU2wtjPwHR1k/sx2iC+B9jrFIi6gowq4TJ8Fvo= X-Google-Smtp-Source: AKy350aGvdFi+RZKjqDDMQzvmBaZ/OiWcvh3hUJR1pdqaSXWZoxf8OpalMpYOO2vxe4OeQZKqKjv7g== X-Received: by 2002:ac2:43a5:0:b0:4b0:2a2f:ea6d with SMTP id t5-20020ac243a5000000b004b02a2fea6dmr444334lfl.35.1680601397119; Tue, 04 Apr 2023 02:43:17 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id l25-20020a19c219000000b004eb258f73a9sm2218443lfc.163.2023.04.04.02.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 02:43:16 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:09 +0200 Subject: [PATCH 7/9] pinctrl: st: Convert to immutable irq_chip MIME-Version: 1.0 Message-Id: <20230403-immutable-irqchips-v1-7-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. I switched to using irqd_to_hwirq() consistently while we are at it. This driver does not use the GPIOCHIP_IRQ_RESOURCE_HELPERS as it defines its own resource reservations, simply in order to turn IRQ lines into inputs on initialization. Also switched the open coded calls to gpiochip_lock_as_irq() to gpiochip_reqres_irq() so we also get the right module reference counting. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 1409339f0279..c1f36b164ea5 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1313,7 +1313,8 @@ static void st_gpio_irq_mask(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct st_gpio_bank *bank = gpiochip_get_data(gc); - writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); + writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } static void st_gpio_irq_unmask(struct irq_data *d) @@ -1321,7 +1322,8 @@ static void st_gpio_irq_unmask(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct st_gpio_bank *bank = gpiochip_get_data(gc); - writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK); } static int st_gpio_irq_request_resources(struct irq_data *d) @@ -1330,14 +1332,14 @@ static int st_gpio_irq_request_resources(struct irq_data *d) st_gpio_direction_input(gc, d->hwirq); - return gpiochip_lock_as_irq(gc, d->hwirq); + return gpiochip_reqres_irq(gc, d->hwirq); } static void st_gpio_irq_release_resources(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - gpiochip_unlock_as_irq(gc, d->hwirq); + gpiochip_relres_irq(gc, d->hwirq); } static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) @@ -1492,7 +1494,7 @@ static const struct gpio_chip st_gpio_template = { .ngpio = ST_GPIO_PINS_PER_BANK, }; -static struct irq_chip st_gpio_irqchip = { +static const struct irq_chip st_gpio_irqchip = { .name = "GPIO", .irq_request_resources = st_gpio_irq_request_resources, .irq_release_resources = st_gpio_irq_release_resources, @@ -1500,7 +1502,7 @@ static struct irq_chip st_gpio_irqchip = { .irq_mask = st_gpio_irq_mask, .irq_unmask = st_gpio_irq_unmask, .irq_set_type = st_gpio_irq_set_type, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, }; static int st_gpiolib_register_bank(struct st_pinctrl *info, @@ -1570,7 +1572,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, } girq = &bank->gpio_chip.irq; - girq->chip = &st_gpio_irqchip; + gpio_irq_chip_set_chip(girq, &st_gpio_irqchip); girq->parent_handler = st_gpio_irq_handler; girq->num_parents = 1; girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),