| Message ID | 20230323102605.1.Ifc1b5be04653f4ab119698a5944bfecded2080d6@changeid |
|---|---|
| State | Accepted |
| Commit | d84f8f2687bdc67f20262e822b206419bcfd0038 |
| Headers | show
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From: Douglas Anderson <dianders@chromium.org>
To: Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Mark Brown <broonie@kernel.org>,
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Cc: Matthias Kaehlcke <mka@chromium.org>,
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linux-spi@vger.kernel.org,
Douglas Anderson <dianders@chromium.org>,
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Rajendra Nayak <rnayak@codeaurora.org>,
Roja Rani Yarubandi <rojay@codeaurora.org>,
linux-kernel@vger.kernel.org
Subject: [PATCH 01/14] arm64: dts: sc7180: Rename qspi data12 as data23
Date: Thu, 23 Mar 2023 10:30:05 -0700
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|
| Series |
Control Quad SPI pinctrl better on Qualcomm Chromebooks
|
expand
|
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ebfa21e9ed8a..fe62ce516c4e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1540,7 +1540,7 @@ qspi_data01: qspi-data01-state { function = "qspi_data"; }; - qspi_data12: qspi-data12-state { + qspi_data23: qspi-data23-state { pins = "gpio66", "gpio67"; function = "qspi_data"; };
There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by: Douglas Anderson <dianders@chromium.org> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)