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CAT:NONE; SFS:(13230025)(4636009)(396003)(136003)(39860400002)(376002)(346002)(451199018)(40470700004)(46966006)(36840700001)(41300700001)(5660300002)(7416002)(8676002)(4326008)(2906002)(40460700003)(36860700001)(82740400003)(356005)(921005)(7636003)(36756003)(86362001)(7696005)(1076003)(107886003)(6666004)(26005)(110136005)(478600001)(70586007)(316002)(8936002)(40480700001)(82310400005)(83380400001)(70206006)(47076005)(426003)(336012)(2616005)(186003)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 01:29:40.4506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e7a71cb-309f-43e8-d315-08db2b3e12c4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6542 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The property is not necessary as it is a constant value and can be hardcoded in the driver code. Signed-off-by: Dipen Patel --- .../timestamp/nvidia,tegra194-hte.yaml | 43 ++----------------- 1 file changed, 4 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index 158dbe58c49f..eafc33e9ae2e 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -42,10 +42,13 @@ properties: nvidia,slices: $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and the value depends on the HTE instance in the chip. + property and the value depends on the HTE instance in the chip. The AON + GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194 + LIC instance has 11 slices and Tegra234 LIC has 17 slices. enum: [3, 11, 17] '#timestamp-cells': @@ -56,46 +59,10 @@ properties: mentioned in the nvidia GPIO device tree binding document. const: 1 -allOf: - - if: - properties: - compatible: - contains: - enum: - - nvidia,tegra194-gte-aon - - nvidia,tegra234-gte-aon - then: - properties: - nvidia,slices: - const: 3 - - - if: - properties: - compatible: - contains: - enum: - - nvidia,tegra194-gte-lic - then: - properties: - nvidia,slices: - const: 11 - - - if: - properties: - compatible: - contains: - enum: - - nvidia,tegra234-gte-lic - then: - properties: - nvidia,slices: - const: 17 - required: - compatible - reg - interrupts - - nvidia,slices - "#timestamp-cells" additionalProperties: false @@ -107,7 +74,6 @@ examples: reg = <0xc1e0000 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <3>; #timestamp-cells = <1>; }; @@ -117,7 +83,6 @@ examples: reg = <0x3aa0000 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <11>; #timestamp-cells = <1>; };