From patchwork Thu Mar 9 07:45:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 661291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0C2BC64EC4 for ; Thu, 9 Mar 2023 07:46:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbjCIHqm (ORCPT ); Thu, 9 Mar 2023 02:46:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230134AbjCIHqN (ORCPT ); Thu, 9 Mar 2023 02:46:13 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4B82DDB1D for ; Wed, 8 Mar 2023 23:46:05 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id f18so1171447lfa.3 for ; Wed, 08 Mar 2023 23:46:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678347965; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=zhXTDSkBpSBmoLnt16h1xxcFV0v4vmTT7mnJI/zNpFI=; b=RdVd7acfqbV/RJ0zljVIdHf8OEekFM1TtLnwjfbFmZBCfpKs48zDqq9jmJ00FNhc3+ /21cJMiUoapp6aQgyYn2yng55EYkn3VehxFmuN1KnP/66ZoKwnbW0Wb8Gmj1f2X4zxlV 6LNliyaEJkqXcqyNFaQ/sM8kHziZlZvQx4gpkJETQSQ83/q9298lWDpGeGdTJmd6GNn4 cGXLY4Hj3atvGpFxTvp1/dXiAJqtNMlGCMP2rAqJr2cXTfR7dDa2I1yjcHTBYj/eTDgY qwctT1YvUcEGtoaxJZUIzCJNr3Gjesc1tFMnBD9WrbkLI9DoPMhpqxXXFYdpMbMvZm76 LW1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678347965; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zhXTDSkBpSBmoLnt16h1xxcFV0v4vmTT7mnJI/zNpFI=; b=xW1xJnu0s7iQf4AJoPjSJKVOZQ266FTsjMxN2j1/UiCw2VUBj6Zlqiiau0JekMhzjl ZgL3hdDVSKEbUwwcZQEk7eJmTiJgceioD4WyrqdNnX2CMGJ9IClnrVoLLkgBZB2i12GY w0nYD/9/w6MnvmOtNm0KHrwJeYwpmJWhIOj00+uJmpJpXs6iK4VqoTScAUeTwRWc9oxz irku+Hkuvp+KibSv90Pktqp8b5jcjL2Ak1MqgQ1bxApIlhVzNnYv6V53Gj2UuM427jv9 zzsqMU27xcbvu9s1284+mhBE4Pk2VzCn6ddkGOlX8PvUn9Rx6tgT/9VIUTEiW0YQWUce G9cA== X-Gm-Message-State: AO0yUKXBiM/sZaNWZv02eWaZdgA3D4X0QO0WWn9bqcq38jKsc7UlxQ5n JJ7wHl8U9C9lKMrbt3s/dYQ9yA== X-Google-Smtp-Source: AK7set+l0IBAcPEMof3/gCWtD/52DgbhsGMf+RINIiurOj/KsNvWkoCxqcEPKNnC9v2V7US9f4a2Fg== X-Received: by 2002:ac2:5630:0:b0:4db:384c:bb8 with SMTP id b16-20020ac25630000000b004db384c0bb8mr5204447lff.69.1678347965235; Wed, 08 Mar 2023 23:46:05 -0800 (PST) Received: from [127.0.1.1] ([85.235.12.219]) by smtp.gmail.com with ESMTPSA id a6-20020a056512020600b004bb766e01a4sm2568972lfo.245.2023.03.08.23.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 23:46:04 -0800 (PST) From: Linus Walleij Date: Thu, 09 Mar 2023 08:45:57 +0100 Subject: [PATCH v3 09/17] gpio: hlwd: Convert to immutable irq_chip MIME-Version: 1.0 Message-Id: <20230215-immutable-chips-v3-9-972542092a77@linaro.org> References: <20230215-immutable-chips-v3-0-972542092a77@linaro.org> In-Reply-To: <20230215-immutable-chips-v3-0-972542092a77@linaro.org> To: Mun Yew Tham , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Alban Bedel , Orson Zhai , Baolin Wang , Chunyan Zhang , Jay Fang , Daniel Palmer , Romain Perier , Santosh Shilimkar , Kevin Hilman , William Breathitt Gray Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-omap@vger.kernel.org, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Acked-by: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/gpio/gpio-hlwd.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-hlwd.c b/drivers/gpio/gpio-hlwd.c index 4e13e937f832..c208ac1c54a6 100644 --- a/drivers/gpio/gpio-hlwd.c +++ b/drivers/gpio/gpio-hlwd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include /* @@ -48,7 +49,7 @@ struct hlwd_gpio { struct gpio_chip gpioc; - struct irq_chip irqc; + struct device *dev; void __iomem *regs; int irq; u32 edge_emulation; @@ -123,6 +124,7 @@ static void hlwd_gpio_irq_mask(struct irq_data *data) mask &= ~BIT(data->hwirq); iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); + gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); } static void hlwd_gpio_irq_unmask(struct irq_data *data) @@ -132,6 +134,7 @@ static void hlwd_gpio_irq_unmask(struct irq_data *data) unsigned long flags; u32 mask; + gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK); mask |= BIT(data->hwirq); @@ -202,6 +205,24 @@ static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) return 0; } +static void hlwd_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) +{ + struct hlwd_gpio *hlwd = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); + + seq_printf(p, dev_name(hlwd->dev)); +} + +static const struct irq_chip hlwd_gpio_irq_chip = { + .irq_mask = hlwd_gpio_irq_mask, + .irq_unmask = hlwd_gpio_irq_unmask, + .irq_enable = hlwd_gpio_irq_enable, + .irq_set_type = hlwd_gpio_irq_set_type, + .irq_print_chip = hlwd_gpio_irq_print_chip, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int hlwd_gpio_probe(struct platform_device *pdev) { struct hlwd_gpio *hlwd; @@ -216,6 +237,8 @@ static int hlwd_gpio_probe(struct platform_device *pdev) if (IS_ERR(hlwd->regs)) return PTR_ERR(hlwd->regs); + hlwd->dev = &pdev->dev; + /* * Claim all GPIOs using the OWNER register. This will not work on * systems where the AHBPROT memory firewall hasn't been configured to @@ -259,14 +282,8 @@ static int hlwd_gpio_probe(struct platform_device *pdev) return hlwd->irq; } - hlwd->irqc.name = dev_name(&pdev->dev); - hlwd->irqc.irq_mask = hlwd_gpio_irq_mask; - hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask; - hlwd->irqc.irq_enable = hlwd_gpio_irq_enable; - hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type; - girq = &hlwd->gpioc.irq; - girq->chip = &hlwd->irqc; + gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip); girq->parent_handler = hlwd_gpio_irqhandler; girq->num_parents = 1; girq->parents = devm_kcalloc(&pdev->dev, 1,